/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Mcu_Ckgen.h                                                                           *
 *  \brief    This file contains interface header for Mcu MCAL driver, ...                             *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/08/01     <td>1.0.0                               *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef MCU_CKGEN_H
#define MCU_CKGEN_H

/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/
#include "Mcu_GeneralTypes.h"
/********************************************************************************************************
 *                                 Global Macro definition                                              *
 *******************************************************************************************************/
#define DOM_PER0_OFF(n)  (0x0U + 20U*(n))

#define FM_DOM_PER0_DOM3_USE_PER  ((uint32)0x3U << 30U)
#define FV_DOM_PER0_DOM3_USE_PER(v) \
  (((uint32)(v) << 30U) & FM_DOM_PER0_DOM3_USE_PER)
#define GFV_DOM_PER0_DOM3_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM3_USE_PER) >> 30U)

#define FM_DOM_PER0_DOM3_PRI_PER  ((uint32)0x3U << 28U)
#define FV_DOM_PER0_DOM3_PRI_PER(v) \
  (((uint32)(v) << 28U) & FM_DOM_PER0_DOM3_PRI_PER)
#define GFV_DOM_PER0_DOM3_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM3_PRI_PER) >> 28U)

#define FM_DOM_PER0_DOM3_NSE_PER  ((uint32)0x3U << 26U)
#define FV_DOM_PER0_DOM3_NSE_PER(v) \
  (((uint32)(v) << 26U) & FM_DOM_PER0_DOM3_NSE_PER)
#define GFV_DOM_PER0_DOM3_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM3_NSE_PER) >> 26U)

#define FM_DOM_PER0_DOM3_SEC_PER  ((uint32)0x3U << 24U)
#define FV_DOM_PER0_DOM3_SEC_PER(v) \
  (((uint32)(v) << 24U) & FM_DOM_PER0_DOM3_SEC_PER)
#define GFV_DOM_PER0_DOM3_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM3_SEC_PER) >> 24U)

#define FM_DOM_PER0_DOM2_USE_PER  ((uint32)0x3U << 22U)
#define FV_DOM_PER0_DOM2_USE_PER(v) \
  (((uint32)(v) << 22U) & FM_DOM_PER0_DOM2_USE_PER)
#define GFV_DOM_PER0_DOM2_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM2_USE_PER) >> 22U)

#define FM_DOM_PER0_DOM2_PRI_PER  ((uint32)0x3U << 20U)
#define FV_DOM_PER0_DOM2_PRI_PER(v) \
  (((uint32)(v) << 20U) & FM_DOM_PER0_DOM2_PRI_PER)
#define GFV_DOM_PER0_DOM2_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM2_PRI_PER) >> 20U)

#define FM_DOM_PER0_DOM2_NSE_PER  ((uint32)0x3U << 18U)
#define FV_DOM_PER0_DOM2_NSE_PER(v) \
  (((uint32)(v) << 18U) & FM_DOM_PER0_DOM2_NSE_PER)
#define GFV_DOM_PER0_DOM2_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM2_NSE_PER) >> 18U)

#define FM_DOM_PER0_DOM2_SEC_PER  ((uint32)0x3U << 16U)
#define FV_DOM_PER0_DOM2_SEC_PER(v) \
  (((uint32)(v) << 16U) & FM_DOM_PER0_DOM2_SEC_PER)
#define GFV_DOM_PER0_DOM2_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM2_SEC_PER) >> 16U)

#define FM_DOM_PER0_DOM1_USE_PER  ((uint32)0x3U << 14U)
#define FV_DOM_PER0_DOM1_USE_PER(v) \
  (((uint32)(v) << 14U) & FM_DOM_PER0_DOM1_USE_PER)
#define GFV_DOM_PER0_DOM1_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM1_USE_PER) >> 14U)

#define FM_DOM_PER0_DOM1_PRI_PER  ((uint32)0x3U << 12U)
#define FV_DOM_PER0_DOM1_PRI_PER(v) \
  (((uint32)(v) << 12U) & FM_DOM_PER0_DOM1_PRI_PER)
#define GFV_DOM_PER0_DOM1_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM1_PRI_PER) >> 12U)

#define FM_DOM_PER0_DOM1_NSE_PER  ((uint32)0x3U << 10U)
#define FV_DOM_PER0_DOM1_NSE_PER(v) \
  (((uint32)(v) << 10U) & FM_DOM_PER0_DOM1_NSE_PER)
#define GFV_DOM_PER0_DOM1_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM1_NSE_PER) >> 10U)

#define FM_DOM_PER0_DOM1_SEC_PER  ((uint32)0x3U << 8U)
#define FV_DOM_PER0_DOM1_SEC_PER(v) \
  (((uint32)(v) << 8U) & FM_DOM_PER0_DOM1_SEC_PER)
#define GFV_DOM_PER0_DOM1_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM1_SEC_PER) >> 8U)

#define FM_DOM_PER0_DOM0_USE_PER  ((uint32)0x3U << 6U)
#define FV_DOM_PER0_DOM0_USE_PER(v) \
  (((uint32)(v) << 6U) & FM_DOM_PER0_DOM0_USE_PER)
#define GFV_DOM_PER0_DOM0_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM0_USE_PER) >> 6U)

#define FM_DOM_PER0_DOM0_PRI_PER  ((uint32)0x3U << 4U)
#define FV_DOM_PER0_DOM0_PRI_PER(v) \
  (((uint32)(v) << 4U) & FM_DOM_PER0_DOM0_PRI_PER)
#define GFV_DOM_PER0_DOM0_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM0_PRI_PER) >> 4U)

#define FM_DOM_PER0_DOM0_NSE_PER  ((uint32)0x3U << 2U)
#define FV_DOM_PER0_DOM0_NSE_PER(v) \
  (((uint32)(v) << 2U) & FM_DOM_PER0_DOM0_NSE_PER)
#define GFV_DOM_PER0_DOM0_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM0_NSE_PER) >> 2U)

#define FM_DOM_PER0_DOM0_SEC_PER  ((uint32)0x3U << 0U)
#define FV_DOM_PER0_DOM0_SEC_PER(v) \
  (((uint32)(v) << 0U) & FM_DOM_PER0_DOM0_SEC_PER)
#define GFV_DOM_PER0_DOM0_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER0_DOM0_SEC_PER) >> 0U)

#define DOM_PER1_OFF(n)  (0x4U + 20U*(n))

#define FM_DOM_PER1_DOM7_USE_PER  ((uint32)0x3U << 30U)
#define FV_DOM_PER1_DOM7_USE_PER(v) \
  (((uint32)(v) << 30U) & FM_DOM_PER1_DOM7_USE_PER)
#define GFV_DOM_PER1_DOM7_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM7_USE_PER) >> 30U)

#define FM_DOM_PER1_DOM7_PRI_PER  ((uint32)0x3U << 28U)
#define FV_DOM_PER1_DOM7_PRI_PER(v) \
  (((uint32)(v) << 28U) & FM_DOM_PER1_DOM7_PRI_PER)
#define GFV_DOM_PER1_DOM7_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM7_PRI_PER) >> 28U)

#define FM_DOM_PER1_DOM7_NSE_PER  ((uint32)0x3U << 26U)
#define FV_DOM_PER1_DOM7_NSE_PER(v) \
  (((uint32)(v) << 26U) & FM_DOM_PER1_DOM7_NSE_PER)
#define GFV_DOM_PER1_DOM7_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM7_NSE_PER) >> 26U)

#define FM_DOM_PER1_DOM7_SEC_PER  ((uint32)0x3U << 24U)
#define FV_DOM_PER1_DOM7_SEC_PER(v) \
  (((uint32)(v) << 24U) & FM_DOM_PER1_DOM7_SEC_PER)
#define GFV_DOM_PER1_DOM7_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM7_SEC_PER) >> 24U)

#define FM_DOM_PER1_DOM6_USE_PER  ((uint32)0x3U << 22U)
#define FV_DOM_PER1_DOM6_USE_PER(v) \
  (((uint32)(v) << 22U) & FM_DOM_PER1_DOM6_USE_PER)
#define GFV_DOM_PER1_DOM6_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM6_USE_PER) >> 22U)

#define FM_DOM_PER1_DOM6_PRI_PER  ((uint32)0x3U << 20U)
#define FV_DOM_PER1_DOM6_PRI_PER(v) \
  (((uint32)(v) << 20U) & FM_DOM_PER1_DOM6_PRI_PER)
#define GFV_DOM_PER1_DOM6_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM6_PRI_PER) >> 20U)

#define FM_DOM_PER1_DOM6_NSE_PER  ((uint32)0x3U << 18U)
#define FV_DOM_PER1_DOM6_NSE_PER(v) \
  (((uint32)(v) << 18U) & FM_DOM_PER1_DOM6_NSE_PER)
#define GFV_DOM_PER1_DOM6_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM6_NSE_PER) >> 18U)

#define FM_DOM_PER1_DOM6_SEC_PER  ((uint32)0x3U << 16U)
#define FV_DOM_PER1_DOM6_SEC_PER(v) \
  (((uint32)(v) << 16U) & FM_DOM_PER1_DOM6_SEC_PER)
#define GFV_DOM_PER1_DOM6_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM6_SEC_PER) >> 16U)

#define FM_DOM_PER1_DOM5_USE_PER  ((uint32)0x3U << 14U)
#define FV_DOM_PER1_DOM5_USE_PER(v) \
  (((uint32)(v) << 14U) & FM_DOM_PER1_DOM5_USE_PER)
#define GFV_DOM_PER1_DOM5_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM5_USE_PER) >> 14U)

#define FM_DOM_PER1_DOM5_PRI_PER  ((uint32)0x3U << 12U)
#define FV_DOM_PER1_DOM5_PRI_PER(v) \
  (((uint32)(v) << 12U) & FM_DOM_PER1_DOM5_PRI_PER)
#define GFV_DOM_PER1_DOM5_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM5_PRI_PER) >> 12U)

#define FM_DOM_PER1_DOM5_NSE_PER  ((uint32)0x3U << 10U)
#define FV_DOM_PER1_DOM5_NSE_PER(v) \
  (((uint32)(v) << 10U) & FM_DOM_PER1_DOM5_NSE_PER)
#define GFV_DOM_PER1_DOM5_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM5_NSE_PER) >> 10U)

#define FM_DOM_PER1_DOM5_SEC_PER  ((uint32)0x3U << 8U)
#define FV_DOM_PER1_DOM5_SEC_PER(v) \
  (((uint32)(v) << 8U) & FM_DOM_PER1_DOM5_SEC_PER)
#define GFV_DOM_PER1_DOM5_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM5_SEC_PER) >> 8U)

#define FM_DOM_PER1_DOM4_USE_PER  ((uint32)0x3U << 6U)
#define FV_DOM_PER1_DOM4_USE_PER(v) \
  (((uint32)(v) << 6U) & FM_DOM_PER1_DOM4_USE_PER)
#define GFV_DOM_PER1_DOM4_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM4_USE_PER) >> 6U)

#define FM_DOM_PER1_DOM4_PRI_PER  ((uint32)0x3U << 4U)
#define FV_DOM_PER1_DOM4_PRI_PER(v) \
  (((uint32)(v) << 4U) & FM_DOM_PER1_DOM4_PRI_PER)
#define GFV_DOM_PER1_DOM4_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM4_PRI_PER) >> 4U)

#define FM_DOM_PER1_DOM4_NSE_PER  ((uint32)0x3U << 2U)
#define FV_DOM_PER1_DOM4_NSE_PER(v) \
  (((uint32)(v) << 2U) & FM_DOM_PER1_DOM4_NSE_PER)
#define GFV_DOM_PER1_DOM4_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM4_NSE_PER) >> 2U)

#define FM_DOM_PER1_DOM4_SEC_PER  ((uint32)0x3U << 0U)
#define FV_DOM_PER1_DOM4_SEC_PER(v) \
  (((uint32)(v) << 0U) & FM_DOM_PER1_DOM4_SEC_PER)
#define GFV_DOM_PER1_DOM4_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER1_DOM4_SEC_PER) >> 0U)

#define DOM_PER2_OFF(n)  (0x8U + 20U*(n))

#define FM_DOM_PER2_DOM11_USE_PER  ((uint32)0x3U << 30U)
#define FV_DOM_PER2_DOM11_USE_PER(v) \
  (((uint32)(v) << 30U) & FM_DOM_PER2_DOM11_USE_PER)
#define GFV_DOM_PER2_DOM11_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM11_USE_PER) >> 30U)

#define FM_DOM_PER2_DOM11_PRI_PER  ((uint32)0x3U << 28U)
#define FV_DOM_PER2_DOM11_PRI_PER(v) \
  (((uint32)(v) << 28U) & FM_DOM_PER2_DOM11_PRI_PER)
#define GFV_DOM_PER2_DOM11_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM11_PRI_PER) >> 28U)

#define FM_DOM_PER2_DOM11_NSE_PER  ((uint32)0x3U << 26U)
#define FV_DOM_PER2_DOM11_NSE_PER(v) \
  (((uint32)(v) << 26U) & FM_DOM_PER2_DOM11_NSE_PER)
#define GFV_DOM_PER2_DOM11_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM11_NSE_PER) >> 26U)

#define FM_DOM_PER2_DOM11_SEC_PER  ((uint32)0x3U << 24U)
#define FV_DOM_PER2_DOM11_SEC_PER(v) \
  (((uint32)(v) << 24U) & FM_DOM_PER2_DOM11_SEC_PER)
#define GFV_DOM_PER2_DOM11_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM11_SEC_PER) >> 24U)

#define FM_DOM_PER2_DOM10_USE_PER  ((uint32)0x3U << 22U)
#define FV_DOM_PER2_DOM10_USE_PER(v) \
  (((uint32)(v) << 22U) & FM_DOM_PER2_DOM10_USE_PER)
#define GFV_DOM_PER2_DOM10_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM10_USE_PER) >> 22U)

#define FM_DOM_PER2_DOM10_PRI_PER  ((uint32)0x3U << 20U)
#define FV_DOM_PER2_DOM10_PRI_PER(v) \
  (((uint32)(v) << 20U) & FM_DOM_PER2_DOM10_PRI_PER)
#define GFV_DOM_PER2_DOM10_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM10_PRI_PER) >> 20U)

#define FM_DOM_PER2_DOM10_NSE_PER  ((uint32)0x3U << 18U)
#define FV_DOM_PER2_DOM10_NSE_PER(v) \
  (((uint32)(v) << 18U) & FM_DOM_PER2_DOM10_NSE_PER)
#define GFV_DOM_PER2_DOM10_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM10_NSE_PER) >> 18U)

#define FM_DOM_PER2_DOM10_SEC_PER  ((uint32)0x3U << 16U)
#define FV_DOM_PER2_DOM10_SEC_PER(v) \
  (((uint32)(v) << 16U) & FM_DOM_PER2_DOM10_SEC_PER)
#define GFV_DOM_PER2_DOM10_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM10_SEC_PER) >> 16U)

#define FM_DOM_PER2_DOM9_USE_PER  ((uint32)0x3U << 14U)
#define FV_DOM_PER2_DOM9_USE_PER(v) \
  (((uint32)(v) << 14U) & FM_DOM_PER2_DOM9_USE_PER)
#define GFV_DOM_PER2_DOM9_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM9_USE_PER) >> 14U)

#define FM_DOM_PER2_DOM9_PRI_PER  ((uint32)0x3U << 12U)
#define FV_DOM_PER2_DOM9_PRI_PER(v) \
  (((uint32)(v) << 12U) & FM_DOM_PER2_DOM9_PRI_PER)
#define GFV_DOM_PER2_DOM9_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM9_PRI_PER) >> 12U)

#define FM_DOM_PER2_DOM9_NSE_PER  ((uint32)0x3U << 10U)
#define FV_DOM_PER2_DOM9_NSE_PER(v) \
  (((uint32)(v) << 10U) & FM_DOM_PER2_DOM9_NSE_PER)
#define GFV_DOM_PER2_DOM9_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM9_NSE_PER) >> 10U)

#define FM_DOM_PER2_DOM9_SEC_PER  ((uint32)0x3U << 8U)
#define FV_DOM_PER2_DOM9_SEC_PER(v) \
  (((uint32)(v) << 8U) & FM_DOM_PER2_DOM9_SEC_PER)
#define GFV_DOM_PER2_DOM9_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM9_SEC_PER) >> 8U)

#define FM_DOM_PER2_DOM8_USE_PER  ((uint32)0x3U << 6U)
#define FV_DOM_PER2_DOM8_USE_PER(v) \
  (((uint32)(v) << 6U) & FM_DOM_PER2_DOM8_USE_PER)
#define GFV_DOM_PER2_DOM8_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM8_USE_PER) >> 6U)

#define FM_DOM_PER2_DOM8_PRI_PER  ((uint32)0x3U << 4U)
#define FV_DOM_PER2_DOM8_PRI_PER(v) \
  (((uint32)(v) << 4U) & FM_DOM_PER2_DOM8_PRI_PER)
#define GFV_DOM_PER2_DOM8_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM8_PRI_PER) >> 4U)

#define FM_DOM_PER2_DOM8_NSE_PER  ((uint32)0x3U << 2U)
#define FV_DOM_PER2_DOM8_NSE_PER(v) \
  (((uint32)(v) << 2U) & FM_DOM_PER2_DOM8_NSE_PER)
#define GFV_DOM_PER2_DOM8_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM8_NSE_PER) >> 2U)

#define FM_DOM_PER2_DOM8_SEC_PER  ((uint32)0x3U << 0U)
#define FV_DOM_PER2_DOM8_SEC_PER(v) \
  (((uint32)(v) << 0U) & FM_DOM_PER2_DOM8_SEC_PER)
#define GFV_DOM_PER2_DOM8_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER2_DOM8_SEC_PER) >> 0U)

#define DOM_PER3_OFF(n)  (0xcU + 20U*(n))

#define FM_DOM_PER3_DOM15_USE_PER  ((uint32)0x3U << 30U)
#define FV_DOM_PER3_DOM15_USE_PER(v) \
  (((uint32)(v) << 30U) & FM_DOM_PER3_DOM15_USE_PER)
#define GFV_DOM_PER3_DOM15_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM15_USE_PER) >> 30U)

#define FM_DOM_PER3_DOM15_PRI_PER  ((uint32)0x3U << 28U)
#define FV_DOM_PER3_DOM15_PRI_PER(v) \
  (((uint32)(v) << 28U) & FM_DOM_PER3_DOM15_PRI_PER)
#define GFV_DOM_PER3_DOM15_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM15_PRI_PER) >> 28U)

#define FM_DOM_PER3_DOM15_NSE_PER  ((uint32)0x3U << 26U)
#define FV_DOM_PER3_DOM15_NSE_PER(v) \
  (((uint32)(v) << 26U) & FM_DOM_PER3_DOM15_NSE_PER)
#define GFV_DOM_PER3_DOM15_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM15_NSE_PER) >> 26U)

#define FM_DOM_PER3_DOM15_SEC_PER  ((uint32)0x3U << 24U)
#define FV_DOM_PER3_DOM15_SEC_PER(v) \
  (((uint32)(v) << 24U) & FM_DOM_PER3_DOM15_SEC_PER)
#define GFV_DOM_PER3_DOM15_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM15_SEC_PER) >> 24U)

#define FM_DOM_PER3_DOM14_USE_PER  ((uint32)0x3U << 22U)
#define FV_DOM_PER3_DOM14_USE_PER(v) \
  (((uint32)(v) << 22U) & FM_DOM_PER3_DOM14_USE_PER)
#define GFV_DOM_PER3_DOM14_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM14_USE_PER) >> 22U)

#define FM_DOM_PER3_DOM14_PRI_PER  ((uint32)0x3U << 20U)
#define FV_DOM_PER3_DOM14_PRI_PER(v) \
  (((uint32)(v) << 20U) & FM_DOM_PER3_DOM14_PRI_PER)
#define GFV_DOM_PER3_DOM14_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM14_PRI_PER) >> 20U)

#define FM_DOM_PER3_DOM14_NSE_PER  ((uint32)0x3U << 18U)
#define FV_DOM_PER3_DOM14_NSE_PER(v) \
  (((uint32)(v) << 18U) & FM_DOM_PER3_DOM14_NSE_PER)
#define GFV_DOM_PER3_DOM14_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM14_NSE_PER) >> 18U)

#define FM_DOM_PER3_DOM14_SEC_PER  ((uint32)0x3U << 16U)
#define FV_DOM_PER3_DOM14_SEC_PER(v) \
  (((uint32)(v) << 16U) & FM_DOM_PER3_DOM14_SEC_PER)
#define GFV_DOM_PER3_DOM14_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM14_SEC_PER) >> 16U)

#define FM_DOM_PER3_DOM13_USE_PER  ((uint32)0x3U << 14U)
#define FV_DOM_PER3_DOM13_USE_PER(v) \
  (((uint32)(v) << 14U) & FM_DOM_PER3_DOM13_USE_PER)
#define GFV_DOM_PER3_DOM13_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM13_USE_PER) >> 14U)

#define FM_DOM_PER3_DOM13_PRI_PER  ((uint32)0x3U << 12U)
#define FV_DOM_PER3_DOM13_PRI_PER(v) \
  (((uint32)(v) << 12U) & FM_DOM_PER3_DOM13_PRI_PER)
#define GFV_DOM_PER3_DOM13_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM13_PRI_PER) >> 12U)

#define FM_DOM_PER3_DOM13_NSE_PER  ((uint32)0x3U << 10U)
#define FV_DOM_PER3_DOM13_NSE_PER(v) \
  (((uint32)(v) << 10U) & FM_DOM_PER3_DOM13_NSE_PER)
#define GFV_DOM_PER3_DOM13_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM13_NSE_PER) >> 10U)

#define FM_DOM_PER3_DOM13_SEC_PER  ((uint32)0x3U << 8U)
#define FV_DOM_PER3_DOM13_SEC_PER(v) \
  (((uint32)(v) << 8U) & FM_DOM_PER3_DOM13_SEC_PER)
#define GFV_DOM_PER3_DOM13_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM13_SEC_PER) >> 8U)

#define FM_DOM_PER3_DOM12_USE_PER  ((uint32)0x3U << 6U)
#define FV_DOM_PER3_DOM12_USE_PER(v) \
  (((uint32)(v) << 6U) & FM_DOM_PER3_DOM12_USE_PER)
#define GFV_DOM_PER3_DOM12_USE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM12_USE_PER) >> 6U)

#define FM_DOM_PER3_DOM12_PRI_PER  ((uint32)0x3U << 4U)
#define FV_DOM_PER3_DOM12_PRI_PER(v) \
  (((uint32)(v) << 4U) & FM_DOM_PER3_DOM12_PRI_PER)
#define GFV_DOM_PER3_DOM12_PRI_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM12_PRI_PER) >> 4U)

#define FM_DOM_PER3_DOM12_NSE_PER  ((uint32)0x3U << 2U)
#define FV_DOM_PER3_DOM12_NSE_PER(v) \
  (((uint32)(v) << 2U) & FM_DOM_PER3_DOM12_NSE_PER)
#define GFV_DOM_PER3_DOM12_NSE_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM12_NSE_PER) >> 2U)

#define FM_DOM_PER3_DOM12_SEC_PER  ((uint32)0x3U << 0U)
#define FV_DOM_PER3_DOM12_SEC_PER(v) \
  (((uint32)(v) << 0U) & FM_DOM_PER3_DOM12_SEC_PER)
#define GFV_DOM_PER3_DOM12_SEC_PER(v) \
  (((uint32)(v) & FM_DOM_PER3_DOM12_SEC_PER) >> 0U)

#define DOM_PER_LOCK_OFF(n)  (0x10U + 20U*(n))

#define BM_DOM_PER_LOCK_DOM15_LOCK  ((uint32)0x01U << 15U)

#define BM_DOM_PER_LOCK_DOM14_LOCK  ((uint32)0x01U << 14U)

#define BM_DOM_PER_LOCK_DOM13_LOCK  ((uint32)0x01U << 13U)

#define BM_DOM_PER_LOCK_DOM12_LOCK  ((uint32)0x01U << 12U)

#define BM_DOM_PER_LOCK_DOM11_LOCK  ((uint32)0x01U << 11U)

#define BM_DOM_PER_LOCK_DOM10_LOCK  ((uint32)0x01U << 10U)

#define BM_DOM_PER_LOCK_DOM9_LOCK  ((uint32)0x01U << 9U)

#define BM_DOM_PER_LOCK_DOM8_LOCK  ((uint32)0x01U << 8U)

#define BM_DOM_PER_LOCK_DOM7_LOCK  ((uint32)0x01U << 7U)

#define BM_DOM_PER_LOCK_DOM6_LOCK  ((uint32)0x01U << 6U)

#define BM_DOM_PER_LOCK_DOM5_LOCK  ((uint32)0x01U << 5U)

#define BM_DOM_PER_LOCK_DOM4_LOCK  ((uint32)0x01U << 4U)

#define BM_DOM_PER_LOCK_DOM3_LOCK  ((uint32)0x01U << 3U)

#define BM_DOM_PER_LOCK_DOM2_LOCK  ((uint32)0x01U << 2U)

#define BM_DOM_PER_LOCK_DOM1_LOCK  ((uint32)0x01U << 1U)

#define BM_DOM_PER_LOCK_DOM0_LOCK  ((uint32)0x01U << 0U)

#define CKGEN_GLB_CTL_RS_OFF  0x200U

#define BM_CKGEN_GLB_CTL_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CKGEN_GLB_CTL_RS_RS  ((uint32)0xfU << 1U)
#define FV_CKGEN_GLB_CTL_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CKGEN_GLB_CTL_RS_RS)
#define GFV_CKGEN_GLB_CTL_RS_RS(v) \
  (((uint32)(v) & FM_CKGEN_GLB_CTL_RS_RS) >> 1U)

#define BM_CKGEN_GLB_CTL_RS_EN  ((uint32)0x01U << 0U)

#define CKGEN_GLB_CTL_OFF  0x204U

#define FM_CKGEN_GLB_CTL_CLK_24M_DIV_C_NUM  ((uint32)0xfU << 28U)
#define FV_CKGEN_GLB_CTL_CLK_24M_DIV_C_NUM(v) \
  (((uint32)(v) << 28U) & FM_CKGEN_GLB_CTL_CLK_24M_DIV_C_NUM)
#define GFV_CKGEN_GLB_CTL_CLK_24M_DIV_C_NUM(v) \
  (((uint32)(v) & FM_CKGEN_GLB_CTL_CLK_24M_DIV_C_NUM) >> 28U)

#define FM_CKGEN_GLB_CTL_CLK_24M_DIV_B_NUM  ((uint32)0x3ffU << 18U)
#define FV_CKGEN_GLB_CTL_CLK_24M_DIV_B_NUM(v) \
  (((uint32)(v) << 18U) & FM_CKGEN_GLB_CTL_CLK_24M_DIV_B_NUM)
#define GFV_CKGEN_GLB_CTL_CLK_24M_DIV_B_NUM(v) \
  (((uint32)(v) & FM_CKGEN_GLB_CTL_CLK_24M_DIV_B_NUM) >> 18U)

#define FM_CKGEN_GLB_CTL_CLK_24M_DIV_A_NUM  ((uint32)0x3ffU << 3U)
#define FV_CKGEN_GLB_CTL_CLK_24M_DIV_A_NUM(v) \
  (((uint32)(v) << 3U) & FM_CKGEN_GLB_CTL_CLK_24M_DIV_A_NUM)
#define GFV_CKGEN_GLB_CTL_CLK_24M_DIV_A_NUM(v) \
  (((uint32)(v) & FM_CKGEN_GLB_CTL_CLK_24M_DIV_A_NUM) >> 3U)

#define BM_CKGEN_GLB_CTL_CLK_24M_DIV_C_DIS  ((uint32)0x01U << 2U)

#define BM_CKGEN_GLB_CTL_CLK_24M_DIV_B_DIS  ((uint32)0x01U << 1U)

#define BM_CKGEN_GLB_CTL_CLK_24M_DIV_A_DIS  ((uint32)0x01U << 0U)

#define CKGEN_GLB_CTL1_OFF  (0x208U)

#define FM_CKGEN_GLB_CTL1_CLK_24M_DIV_B_NUM  ((uint32)0xffffU << 16U)
#define FV_CKGEN_GLB_CTL1_CLK_24M_DIV_B_NUM(v) \
  (((uint32)(v) << 16U) & FM_CKGEN_GLB_CTL1_CLK_24M_DIV_B_NUM)
#define GFV_CKGEN_GLB_CTL1_CLK_24M_DIV_B_NUM(v) \
  (((uint32)(v) & FM_CKGEN_GLB_CTL1_CLK_24M_DIV_B_NUM) >> 16U)

#define FM_CKGEN_GLB_CTL1_CLK_24M_DIV_A_NUM  ((uint32)0xffffU << 0U)
#define FV_CKGEN_GLB_CTL1_CLK_24M_DIV_A_NUM(v) \
  (((uint32)(v) << 0U) & FM_CKGEN_GLB_CTL1_CLK_24M_DIV_A_NUM)
#define GFV_CKGEN_GLB_CTL1_CLK_24M_DIV_A_NUM(v) \
  (((uint32)(v) & FM_CKGEN_GLB_CTL1_CLK_24M_DIV_A_NUM) >> 0U)

#define CKGEN_SUP_DOM_OFF  0x300U

#define BM_CKGEN_SUP_DOM_LOCK  ((uint32)0x01U << 31U)

#define FM_CKGEN_SUP_DOM_PPROT  ((uint32)0x3U << 5U)
#define FV_CKGEN_SUP_DOM_PPROT(v) \
  (((uint32)(v) << 5U) & FM_CKGEN_SUP_DOM_PPROT)
#define GFV_CKGEN_SUP_DOM_PPROT(v) \
  (((uint32)(v) & FM_CKGEN_SUP_DOM_PPROT) >> 5U)

#define BM_CKGEN_SUP_DOM_SEC_EN  ((uint32)0x01U << 4U)

#define FM_CKGEN_SUP_DOM_DID  ((uint32)0xfU << 0U)
#define FV_CKGEN_SUP_DOM_DID(v) \
  (((uint32)(v) << 0U) & FM_CKGEN_SUP_DOM_DID)
#define GFV_CKGEN_SUP_DOM_DID(v) \
  (((uint32)(v) & FM_CKGEN_SUP_DOM_DID) >> 0U)

#define CKGEN_RES_RS_OFF  0x400U

#define BM_CKGEN_RES_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CKGEN_RES_RS_RS  ((uint32)0xfU << 1U)
#define FV_CKGEN_RES_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CKGEN_RES_RS_RS)
#define GFV_CKGEN_RES_RS_RS(v) \
  (((uint32)(v) & FM_CKGEN_RES_RS_RS) >> 1U)

#define BM_CKGEN_RES_RS_EN  ((uint32)0x01U << 0U)

#define CKGEN_RES_OFF  0x404U

#define FM_CKGEN_RES_RES  ((uint32)0xffffffffU << 0U)
#define FV_CKGEN_RES_RES(v) \
  (((uint32)(v) << 0U) & FM_CKGEN_RES_RES)
#define GFV_CKGEN_RES_RES(v) \
  (((uint32)(v) & FM_CKGEN_RES_RES) >> 0U)

#define CKGEN_MISC_RS_OFF  0x500U

#define BM_CKGEN_MISC_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CKGEN_MISC_RS_RS  ((uint32)0xfU << 1U)
#define FV_CKGEN_MISC_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CKGEN_MISC_RS_RS)
#define GFV_CKGEN_MISC_RS_RS(v) \
  (((uint32)(v) & FM_CKGEN_MISC_RS_RS) >> 1U)

#define BM_CKGEN_MISC_RS_EN  ((uint32)0x01U << 0U)

#define CKGEN_MISC_OFF  0x504U

#define FM_CKGEN_MISC_MISC  ((uint32)0xffffffffU << 0U)
#define FV_CKGEN_MISC_MISC(v) \
  (((uint32)(v) << 0U) & FM_CKGEN_MISC_MISC)
#define GFV_CKGEN_MISC_MISC(v) \
  (((uint32)(v) & FM_CKGEN_MISC_MISC) >> 0U)

#define CKGEN_MISC_MON_OFF  0x508U

#define FM_CKGEN_MISC_MON_MON  ((uint32)0xffffffffU << 0U)
#define FV_CKGEN_MISC_MON_MON(v) \
  (((uint32)(v) << 0U) & FM_CKGEN_MISC_MON_MON)
#define GFV_CKGEN_MISC_MON_MON(v) \
  (((uint32)(v) & FM_CKGEN_MISC_MON_MON) >> 0U)

#define IP_SLICE_RS_OFF(n)  (0x1000U + 16U*(n))

#define BM_IP_SLICE_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_IP_SLICE_RS_RS  ((uint32)0xfU << 1U)
#define FV_IP_SLICE_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_IP_SLICE_RS_RS)
#define GFV_IP_SLICE_RS_RS(v) \
  (((uint32)(v) & FM_IP_SLICE_RS_RS) >> 1U)

#define BM_IP_SLICE_RS_EN  ((uint32)0x01U << 0U)

#define IP_SLICE_CTL_OFF(n)  (0x1004U + (16U*(n)))

#define BM_IP_SLICE_CTL_HW_CG_EN_STATUS  ((uint32)0x01U << 31U)

#define BM_IP_SLICE_CTL_MAIN_EN_STATUS  ((uint32)0x01U << 30U)

#define BM_IP_SLICE_CTL_PRE_EN_STATUS  ((uint32)0x01U << 29U)

#define BM_IP_SLICE_CTL_DIV_CHG_BUSY  ((uint32)0x01U << 28U)

#define BM_IP_SLICE_CTL_MUX_D0_ACTIVE  ((uint32)0x01U << 27U)

#define FM_IP_SLICE_CTL_DIV_NUM  ((uint32)0xffU << 8U)
#define FV_IP_SLICE_CTL_DIV_NUM(v) \
  (((uint32)(v) << 8U) & FM_IP_SLICE_CTL_DIV_NUM)
#define GFV_IP_SLICE_CTL_DIV_NUM(v) \
  (((uint32)(v) & FM_IP_SLICE_CTL_DIV_NUM) >> 8U)

#define BM_IP_SLICE_CTL_HW_DIS_EN  ((uint32)0x01U << 7U)

#define BM_IP_SLICE_CTL_DBG_EN  ((uint32)0x01U << 6U)

#define BM_IP_SLICE_CTL_MAIN_EN  ((uint32)0x01U << 5U)

#define BM_IP_SLICE_CTL_PRE_EN  ((uint32)0x01U << 4U)

#define FM_IP_SLICE_CTL_CLK_SRC_SEL  ((uint32)0x7U << 0U)
#define FV_IP_SLICE_CTL_CLK_SRC_SEL(v) \
  (((uint32)(v) << 0U) & FM_IP_SLICE_CTL_CLK_SRC_SEL)
#define GFV_IP_SLICE_CTL_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_IP_SLICE_CTL_CLK_SRC_SEL) >> 0U)

#define BM_IP_SLICE_CTL_CLK_SRC_SEL_CLKIN4  ((uint32)0x1U << 2U)

#define IP_SLICE_MON_CTL_OFF(n)  (0x1008U + (16U*(n)))

#define FM_IP_SLICE_MON_CTL_FREQ_MON  ((uint32)0xffffU << 16U)
#define FV_IP_SLICE_MON_CTL_FREQ_MON(v) \
  (((uint32)(v) << 16U) & FM_IP_SLICE_MON_CTL_FREQ_MON)
#define GFV_IP_SLICE_MON_CTL_FREQ_MON(v) \
  (((uint32)(v) & FM_IP_SLICE_MON_CTL_FREQ_MON) >> 16U)

#define BM_IP_SLICE_MON_CTL_MON_EN_STA  ((uint32)0x01U << 9U)

#define BM_IP_SLICE_MON_CTL_FREQ_MON_UPD  ((uint32)0x01U << 8U)

#define BM_IP_SLICE_MON_CTL_HIB_EXP  ((uint32)0x01U << 4U)

#define BM_IP_SLICE_MON_CTL_SLP_EXP  ((uint32)0x01U << 3U)

#define BM_IP_SLICE_MON_CTL_MON_CLK_SRC_SEL  ((uint32)0x01U << 2U)

#define BM_IP_SLICE_MON_CTL_ACTIVE_DISABLE  ((uint32)0x01U << 1U)

#define BM_IP_SLICE_MON_CTL_MON_EN  ((uint32)0x01U << 0U)

#define IP_SLICE_MON_THRD_OFF(n)  (0x100cU + (16U*(n)))

#define FM_IP_SLICE_MON_THRD_HIGH_THRD  ((uint32)0xffffU << 16U)
#define FV_IP_SLICE_MON_THRD_HIGH_THRD(v) \
  (((uint32)(v) << 16U) & FM_IP_SLICE_MON_THRD_HIGH_THRD)
#define GFV_IP_SLICE_MON_THRD_HIGH_THRD(v) \
  (((uint32)(v) & FM_IP_SLICE_MON_THRD_HIGH_THRD) >> 16U)

#define FM_IP_SLICE_MON_THRD_LOW_THRD  ((uint32)0xffffU << 0U)
#define FV_IP_SLICE_MON_THRD_LOW_THRD(v) \
  (((uint32)(v) << 0U) & FM_IP_SLICE_MON_THRD_LOW_THRD)
#define GFV_IP_SLICE_MON_THRD_LOW_THRD(v) \
  (((uint32)(v) & FM_IP_SLICE_MON_THRD_LOW_THRD) >> 0U)

#define BUS_SLICE_RS_OFF(n)  (0x2000U + 40U*(n))

#define BM_BUS_SLICE_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_BUS_SLICE_RS_RS  ((uint32)0xfU << 1U)
#define FV_BUS_SLICE_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_BUS_SLICE_RS_RS)
#define GFV_BUS_SLICE_RS_RS(v) \
  (((uint32)(v) & FM_BUS_SLICE_RS_RS) >> 1U)

#define BM_BUS_SLICE_RS_EN  ((uint32)0x01U << 0U)

#define BUS_SLICE_CTL_OFF(n)  (0x2004U + (40U*(n)))

#define BM_BUS_SLICE_CTL_HW_CG_EN_STATUS  ((uint32)0x01U << 31U)

#define BM_BUS_SLICE_CTL_MAIN_EN_STATUS  ((uint32)0x01U << 30U)

#define BM_BUS_SLICE_CTL_PRE_EN_STATUS  ((uint32)0x01U << 29U)

#define BM_BUS_SLICE_CTL_DIV_CHG_BUSY  ((uint32)0x01U << 28U)

#define BM_BUS_SLICE_CTL_POST_MUX_D0_ACTIVE  ((uint32)0x01U << 27U)

#define BM_BUS_SLICE_CTL_PRE_MUX_D0_ACTIVE  ((uint32)0x01U << 26U)

#define FM_BUS_SLICE_CTL_DIV_NUM  ((uint32)0x1fU << 8U)
#define FV_BUS_SLICE_CTL_DIV_NUM(v) \
  (((uint32)(v) << 8U) & FM_BUS_SLICE_CTL_DIV_NUM)
#define GFV_BUS_SLICE_CTL_DIV_NUM(v) \
  (((uint32)(v) & FM_BUS_SLICE_CTL_DIV_NUM) >> 8U)

#define BM_BUS_SLICE_CTL_HW_DIS_EN  ((uint32)0x01U << 7U)

#define BM_BUS_SLICE_CTL_DBG_EN  ((uint32)0x01U << 6U)

#define BM_BUS_SLICE_CTL_MAIN_EN  ((uint32)0x01U << 5U)

#define BM_BUS_SLICE_CTL_PRE_EN  ((uint32)0x01U << 4U)

#define FM_BUS_SLICE_CTL_CLK_SRC_SEL  ((uint32)0xfU << 0U)
#define FV_BUS_SLICE_CTL_CLK_SRC_SEL(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_CTL_CLK_SRC_SEL)
#define GFV_BUS_SLICE_CTL_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_BUS_SLICE_CTL_CLK_SRC_SEL) >> 0U)

#define BM_BUS_SLICE_CTL_CLK_SRC_SEL_BIT3  ((uint32)0x1U << 3U)

#define BM_BUS_SLICE_CTL_CLK_SRC_SEL_CLKIN4  ((uint32)0x1U << 2U)

#define BUS_SLICE_SYNC_CTL_OFF(n)  (0x2008U + (40U*(n)))

#define BM_BUS_SLICE_SYNC_CTL_DIV_Q_CHG_BUSY  ((uint32)0x01U << 31U)

#define BM_BUS_SLICE_SYNC_CTL_DIV_P_CHG_BUSY  ((uint32)0x01U << 30U)

#define BM_BUS_SLICE_SYNC_CTL_DIV_N_CHG_BUSY  ((uint32)0x01U << 29U)

#define BM_BUS_SLICE_SYNC_CTL_DIV_M_CHG_BUSY  ((uint32)0x01U << 28U)

#define FM_BUS_SLICE_SYNC_CTL_DIV_Q_NUM  ((uint32)0xfU << 12U)
#define FV_BUS_SLICE_SYNC_CTL_DIV_Q_NUM(v) \
  (((uint32)(v) << 12U) & FM_BUS_SLICE_SYNC_CTL_DIV_Q_NUM)
#define GFV_BUS_SLICE_SYNC_CTL_DIV_Q_NUM(v) \
  (((uint32)(v) & FM_BUS_SLICE_SYNC_CTL_DIV_Q_NUM) >> 12U)

#define FM_BUS_SLICE_SYNC_CTL_DIV_P_NUM  ((uint32)0xfU << 8U)
#define FV_BUS_SLICE_SYNC_CTL_DIV_P_NUM(v) \
  (((uint32)(v) << 8U) & FM_BUS_SLICE_SYNC_CTL_DIV_P_NUM)
#define GFV_BUS_SLICE_SYNC_CTL_DIV_P_NUM(v) \
  (((uint32)(v) & FM_BUS_SLICE_SYNC_CTL_DIV_P_NUM) >> 8U)

#define FM_BUS_SLICE_SYNC_CTL_DIV_N_NUM  ((uint32)0xfU << 4U)
#define FV_BUS_SLICE_SYNC_CTL_DIV_N_NUM(v) \
  (((uint32)(v) << 4U) & FM_BUS_SLICE_SYNC_CTL_DIV_N_NUM)
#define GFV_BUS_SLICE_SYNC_CTL_DIV_N_NUM(v) \
  (((uint32)(v) & FM_BUS_SLICE_SYNC_CTL_DIV_N_NUM) >> 4U)

#define FM_BUS_SLICE_SYNC_CTL_DIV_M_NUM  ((uint32)0xfU << 0U)
#define FV_BUS_SLICE_SYNC_CTL_DIV_M_NUM(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_SYNC_CTL_DIV_M_NUM)
#define GFV_BUS_SLICE_SYNC_CTL_DIV_M_NUM(v) \
  (((uint32)(v) & FM_BUS_SLICE_SYNC_CTL_DIV_M_NUM) >> 0U)

#define BUS_SLICE_MON_CTL_0_OFF(n)  (0x200cU + (40U*(n)))

#define BM_BUS_SLICE_MON_CTL_0_FREQ_MON_3_UPD  ((uint32)0x01U << 11U)

#define BM_BUS_SLICE_MON_CTL_0_FREQ_MON_2_UPD  ((uint32)0x01U << 10U)

#define BM_BUS_SLICE_MON_CTL_0_FREQ_MON_1_UPD  ((uint32)0x01U << 9U)

#define BM_BUS_SLICE_MON_CTL_0_FREQ_MON_0_UPD  ((uint32)0x01U << 8U)

#define BM_BUS_SLICE_MON_CTL_0_MON_EN_STA  ((uint32)0x01U << 5U)

#define BM_BUS_SLICE_MON_CTL_0_HIB_EXP  ((uint32)0x01U << 4U)

#define BM_BUS_SLICE_MON_CTL_0_SLP_EXP  ((uint32)0x01U << 3U)

#define BM_BUS_SLICE_MON_CTL_0_MON_CLK_SRC_SEL  ((uint32)0x01U << 2U)

#define BM_BUS_SLICE_MON_CTL_0_ACTIVE_DISABLE  ((uint32)0x01U << 1U)

#define BM_BUS_SLICE_MON_CTL_0_MON_EN  ((uint32)0x01U << 0U)

#define BUS_SLICE_MON_CTL_1_OFF(n)  (0x2010U + (40U*(n)))

#define FM_BUS_SLICE_MON_CTL_1_FREQ_MON_1  ((uint32)0xffffU << 16U)
#define FV_BUS_SLICE_MON_CTL_1_FREQ_MON_1(v) \
  (((uint32)(v) << 16U) & FM_BUS_SLICE_MON_CTL_1_FREQ_MON_1)
#define GFV_BUS_SLICE_MON_CTL_1_FREQ_MON_1(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_CTL_1_FREQ_MON_1) >> 16U)

#define FM_BUS_SLICE_MON_CTL_1_FREQ_MON_0  ((uint32)0xffffU << 0U)
#define FV_BUS_SLICE_MON_CTL_1_FREQ_MON_0(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_MON_CTL_1_FREQ_MON_0)
#define GFV_BUS_SLICE_MON_CTL_1_FREQ_MON_0(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_CTL_1_FREQ_MON_0) >> 0U)

#define BUS_SLICE_MON_CTL_2_OFF(n)  (0x2014U + (40U*(n)))

#define FM_BUS_SLICE_MON_CTL_2_FREQ_MON_3  ((uint32)0xffffU << 16U)
#define FV_BUS_SLICE_MON_CTL_2_FREQ_MON_3(v) \
  (((uint32)(v) << 16U) & FM_BUS_SLICE_MON_CTL_2_FREQ_MON_3)
#define GFV_BUS_SLICE_MON_CTL_2_FREQ_MON_3(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_CTL_2_FREQ_MON_3) >> 16U)

#define FM_BUS_SLICE_MON_CTL_2_FREQ_MON_2  ((uint32)0xffffU << 0U)
#define FV_BUS_SLICE_MON_CTL_2_FREQ_MON_2(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_MON_CTL_2_FREQ_MON_2)
#define GFV_BUS_SLICE_MON_CTL_2_FREQ_MON_2(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_CTL_2_FREQ_MON_2) >> 0U)

#define BUS_SLICE_MON_0_THRD_OFF(n)  (0x2018U + (40U*(n)))

#define FM_BUS_SLICE_MON_0_THRD_HIGH_THRD  ((uint32)0xffffU << 16U)
#define FV_BUS_SLICE_MON_0_THRD_HIGH_THRD(v) \
  (((uint32)(v) << 16U) & FM_BUS_SLICE_MON_0_THRD_HIGH_THRD)
#define GFV_BUS_SLICE_MON_0_THRD_HIGH_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_0_THRD_HIGH_THRD) >> 16U)

#define FM_BUS_SLICE_MON_0_THRD_LOW_THRD  ((uint32)0xffffU << 0U)
#define FV_BUS_SLICE_MON_0_THRD_LOW_THRD(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_MON_0_THRD_LOW_THRD)
#define GFV_BUS_SLICE_MON_0_THRD_LOW_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_0_THRD_LOW_THRD) >> 0U)

#define BUS_SLICE_MON_1_THRD_OFF(n)  (0x201cU + (40U*(n)))

#define FM_BUS_SLICE_MON_1_THRD_HIGH_THRD  ((uint32)0xffffU << 16U)
#define FV_BUS_SLICE_MON_1_THRD_HIGH_THRD(v) \
  (((uint32)(v) << 16U) & FM_BUS_SLICE_MON_1_THRD_HIGH_THRD)
#define GFV_BUS_SLICE_MON_1_THRD_HIGH_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_1_THRD_HIGH_THRD) >> 16U)

#define FM_BUS_SLICE_MON_1_THRD_LOW_THRD  ((uint32)0xffffU << 0U)
#define FV_BUS_SLICE_MON_1_THRD_LOW_THRD(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_MON_1_THRD_LOW_THRD)
#define GFV_BUS_SLICE_MON_1_THRD_LOW_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_1_THRD_LOW_THRD) >> 0U)

#define BUS_SLICE_MON_2_THRD_OFF(n)  (0x2020U + (40U*(n)))

#define FM_BUS_SLICE_MON_2_THRD_HIGH_THRD  ((uint32)0xffffU << 16U)
#define FV_BUS_SLICE_MON_2_THRD_HIGH_THRD(v) \
  (((uint32)(v) << 16U) & FM_BUS_SLICE_MON_2_THRD_HIGH_THRD)
#define GFV_BUS_SLICE_MON_2_THRD_HIGH_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_2_THRD_HIGH_THRD) >> 16U)

#define FM_BUS_SLICE_MON_2_THRD_LOW_THRD  ((uint32)0xffffU << 0U)
#define FV_BUS_SLICE_MON_2_THRD_LOW_THRD(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_MON_2_THRD_LOW_THRD)
#define GFV_BUS_SLICE_MON_2_THRD_LOW_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_2_THRD_LOW_THRD) >> 0U)

#define BUS_SLICE_MON_3_THRD_OFF(n)  (0x2024U + (40U*(n)))

#define FM_BUS_SLICE_MON_3_THRD_HIGH_THRD  ((uint32)0xffffU << 16U)
#define FV_BUS_SLICE_MON_3_THRD_HIGH_THRD(v) \
  (((uint32)(v) << 16U) & FM_BUS_SLICE_MON_3_THRD_HIGH_THRD)
#define GFV_BUS_SLICE_MON_3_THRD_HIGH_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_3_THRD_HIGH_THRD) >> 16U)

#define FM_BUS_SLICE_MON_3_THRD_LOW_THRD  ((uint32)0xffffU << 0U)
#define FV_BUS_SLICE_MON_3_THRD_LOW_THRD(v) \
  (((uint32)(v) << 0U) & FM_BUS_SLICE_MON_3_THRD_LOW_THRD)
#define GFV_BUS_SLICE_MON_3_THRD_LOW_THRD(v) \
  (((uint32)(v) & FM_BUS_SLICE_MON_3_THRD_LOW_THRD) >> 0U)

#define CORE_SLICE_RS_OFF(n)  (0x3000U + 16U*(n))

#define BM_CORE_SLICE_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CORE_SLICE_RS_RS  ((uint32)0xfU << 1U)
#define FV_CORE_SLICE_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CORE_SLICE_RS_RS)
#define GFV_CORE_SLICE_RS_RS(v) \
  (((uint32)(v) & FM_CORE_SLICE_RS_RS) >> 1U)

#define BM_CORE_SLICE_RS_EN  ((uint32)0x01U << 0U)

#define CORE_SLICE_CTL_OFF(n)  (0x3004U + 16U*(n))

#define BM_CORE_SLICE_CTL_HW_CG_EN_STATUS  ((uint32)0x01U << 31U)

#define BM_CORE_SLICE_CTL_MAIN_EN_STATUS  ((uint32)0x01U << 30U)

#define BM_CORE_SLICE_CTL_PRE_EN_STATUS  ((uint32)0x01U << 29U)

#define BM_CORE_SLICE_CTL_DIV_CHG_BUSY  ((uint32)0x01U << 28U)

#define BM_CORE_SLICE_CTL_MUX_D0_ACTIVE  ((uint32)0x01U << 27U)

#define FM_CORE_SLICE_CTL_DIV_NUM  ((uint32)0x1fU << 8U)
#define FV_CORE_SLICE_CTL_DIV_NUM(v) \
  (((uint32)(v) << 8U) & FM_CORE_SLICE_CTL_DIV_NUM)
#define GFV_CORE_SLICE_CTL_DIV_NUM(v) \
  (((uint32)(v) & FM_CORE_SLICE_CTL_DIV_NUM) >> 8U)

#define BM_CORE_SLICE_CTL_HW_DIS_EN  ((uint32)0x01U << 7U)

#define BM_CORE_SLICE_CTL_DBG_EN  ((uint32)0x01U << 6U)

#define BM_CORE_SLICE_CTL_MAIN_EN  ((uint32)0x01U << 5U)

#define BM_CORE_SLICE_CTL_PRE_EN  ((uint32)0x01U << 4U)

#define FM_CORE_SLICE_CTL_CLK_SRC_SEL  ((uint32)0x7U << 0U)
#define FV_CORE_SLICE_CTL_CLK_SRC_SEL(v) \
  (((uint32)(v) << 0U) & FM_CORE_SLICE_CTL_CLK_SRC_SEL)
#define GFV_CORE_SLICE_CTL_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_CORE_SLICE_CTL_CLK_SRC_SEL) >> 0U)

#define CORE_SLICE_MON_CTL_OFF(n)  (0x3008U + 16U*(n))

#define FM_CORE_SLICE_MON_CTL_FREQ_MON  ((uint32)0xffffU << 16U)
#define FV_CORE_SLICE_MON_CTL_FREQ_MON(v) \
  (((uint32)(v) << 16U) & FM_CORE_SLICE_MON_CTL_FREQ_MON)
#define GFV_CORE_SLICE_MON_CTL_FREQ_MON(v) \
  (((uint32)(v) & FM_CORE_SLICE_MON_CTL_FREQ_MON) >> 16U)

#define BM_CORE_SLICE_MON_CTL_MON_EN_STA  ((uint32)0x01U << 9U)

#define BM_CORE_SLICE_MON_CTL_FREQ_MON_UPD  ((uint32)0x01U << 8U)

#define BM_CORE_SLICE_MON_CTL_HIB_EXP  ((uint32)0x01U << 4U)

#define BM_CORE_SLICE_MON_CTL_SLP_EXP  ((uint32)0x01U << 3U)

#define BM_CORE_SLICE_MON_CTL_MON_CLK_SRC_SEL  ((uint32)0x01U << 2U)

#define BM_CORE_SLICE_MON_CTL_ACTIVE_DISABLE  ((uint32)0x01U << 1U)

#define BM_CORE_SLICE_MON_CTL_MON_EN  ((uint32)0x01U << 0U)

#define CORE_SLICE_MON_THRD_OFF(n)  (0x300cU + 16U*(n))

#define FM_CORE_SLICE_MON_THRD_HIGH_THRD  ((uint32)0xffffU << 16U)
#define FV_CORE_SLICE_MON_THRD_HIGH_THRD(v) \
  (((uint32)(v) << 16U) & FM_CORE_SLICE_MON_THRD_HIGH_THRD)
#define GFV_CORE_SLICE_MON_THRD_HIGH_THRD(v) \
  (((uint32)(v) & FM_CORE_SLICE_MON_THRD_HIGH_THRD) >> 16U)

#define FM_CORE_SLICE_MON_THRD_LOW_THRD  ((uint32)0xffffU << 0U)
#define FV_CORE_SLICE_MON_THRD_LOW_THRD(v) \
  (((uint32)(v) << 0U) & FM_CORE_SLICE_MON_THRD_LOW_THRD)
#define GFV_CORE_SLICE_MON_THRD_LOW_THRD(v) \
  (((uint32)(v) & FM_CORE_SLICE_MON_THRD_LOW_THRD) >> 0U)

#define PCG_RS_OFF(n)  (0x4000U + 8U*(n))

#define BM_PCG_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_PCG_RS_RS  ((uint32)0xfU << 1U)
#define FV_PCG_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_PCG_RS_RS)
#define GFV_PCG_RS_RS(v) \
  (((uint32)(v) & FM_PCG_RS_RS) >> 1U)

#define BM_PCG_RS_EN  ((uint32)0x01U << 0U)

#define PCG_CTL_OFF(n)  (0x4004U + (8U*(n)))

#define BM_PCG_CTL_LP_DBG_EN  ((uint32)0x01U << 16U)

#define BM_PCG_CTL_LP_MASK  ((uint32)0x01U << 8U)

#define BM_PCG_CTL_DBG_EN  ((uint32)0x01U << 6U)

#define BM_PCG_CTL_CG_GATED  ((uint32)0x01U << 5U)

#define BM_PCG_CTL_ACTIVE_MON_STA  ((uint32)0x01U << 4U)

#define BM_PCG_CTL_ACTIVE_MON_EN  ((uint32)0x01U << 3U)

#define BM_PCG_CTL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_PCG_CTL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_PCG_CTL_RUN_MODE  ((uint32)0x01U << 0U)

#define BCG_RS_OFF(n)  (0x5000U + 8U*(n))

#define BM_BCG_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_BCG_RS_RS  ((uint32)0xfU << 1U)
#define FV_BCG_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_BCG_RS_RS)
#define GFV_BCG_RS_RS(v) \
  (((uint32)(v) & FM_BCG_RS_RS) >> 1U)

#define BM_BCG_RS_EN  ((uint32)0x01U << 0U)

#define BCG_CTL_OFF(n)  (0x5004U + (8U*(n)))

#define BM_BCG_CTL_LP_DBG_EN  ((uint32)0x01U << 16U)

#define BM_BCG_CTL_LP_MASK  ((uint32)0x01U << 8U)

#define BM_BCG_CTL_DBG_EN  ((uint32)0x01U << 6U)

#define BM_BCG_CTL_CG_GATED  ((uint32)0x01U << 5U)

#define BM_BCG_CTL_ACTIVE_MON_STA  ((uint32)0x01U << 4U)

#define BM_BCG_CTL_ACTIVE_MON_EN  ((uint32)0x01U << 3U)

#define BM_BCG_CTL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_BCG_CTL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_BCG_CTL_RUN_MODE  ((uint32)0x01U << 0U)

#define CCG_RS_OFF(n)  (0x6000U + 8U*(n))

#define BM_CCG_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CCG_RS_RS  ((uint32)0xfU << 1U)
#define FV_CCG_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CCG_RS_RS)
#define GFV_CCG_RS_RS(v) \
  (((uint32)(v) & FM_CCG_RS_RS) >> 1U)

#define BM_CCG_RS_EN  ((uint32)0x01U << 0U)

#define CCG_CTL_OFF(n)  (0x6004U + 8U*(n))

#define BM_CCG_CTL_LP_DBG_EN  ((uint32)0x01U << 16U)

#define BM_CCG_CTL_LP_MASK  ((uint32)0x01U << 8U)

#define BM_CCG_CTL_DBG_EN  ((uint32)0x01U << 6U)

#define BM_CCG_CTL_CG_GATED  ((uint32)0x01U << 5U)

#define BM_CCG_CTL_ACTIVE_MON_STA  ((uint32)0x01U << 4U)

#define BM_CCG_CTL_ACTIVE_MON_EN  ((uint32)0x01U << 3U)

#define BM_CCG_CTL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_CCG_CTL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_CCG_CTL_RUN_MODE  ((uint32)0x01U << 0U)

#define PLL_RS_OFF(n)  (0x7000U + 12U*(n))

#define BM_PLL_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_PLL_RS_RS  ((uint32)0xfU << 1U)
#define FV_PLL_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_PLL_RS_RS)
#define GFV_PLL_RS_RS(v) \
  (((uint32)(v) & FM_PLL_RS_RS) >> 1U)

#define BM_PLL_RS_EN  ((uint32)0x01U << 0U)

#define CKGEN_PLL_CTL_OFF(n)  (0x7004U + (12U*(n)))

#define BM_PLL_CTL_LP_DBG_EN  ((uint32)0x01U << 16U)

#define BM_PLL_CTL_PD_SLP_MODE  ((uint32)0x01U << 6U)

#define BM_PLL_CTL_PD_HIB_MODE  ((uint32)0x01U << 5U)

#define BM_PLL_CTL_PD_RUN_MODE  ((uint32)0x01U << 4U)

#define BM_PLL_CTL_IGNORE_PLL  ((uint32)0x01U << 3U)

#define BM_PLL_CTL_CLK_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_PLL_CTL_CLK_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_PLL_CTL_CLK_RUN_MODE  ((uint32)0x01U << 0U)

#define PLL_MON_CTL_OFF(n)  (0x7008U + (12U*(n)))

#define BM_PLL_MON_CTL_PLL_CLK_RDY  ((uint32)0x01U << 31U)

#define FM_PLL_MON_CTL_TOUT_VAL  ((uint32)0xffffU << 8U)
#define FV_PLL_MON_CTL_TOUT_VAL(v) \
  (((uint32)(v) << 8U) & FM_PLL_MON_CTL_TOUT_VAL)
#define GFV_PLL_MON_CTL_TOUT_VAL(v) \
  (((uint32)(v) & FM_PLL_MON_CTL_TOUT_VAL) >> 8U)

#define BM_PLL_MON_CTL_MON_EN  ((uint32)0x01U << 0U)

#define XTAL_RS_OFF(n)  (0x7500U + 12U*(n))

#define BM_XTAL_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_XTAL_RS_RS  ((uint32)0xfU << 1U)
#define FV_XTAL_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_XTAL_RS_RS)
#define GFV_XTAL_RS_RS(v) \
  (((uint32)(v) & FM_XTAL_RS_RS) >> 1U)

#define BM_XTAL_RS_EN  ((uint32)0x01U << 0U)

#define XTAL_CTL_OFF(n)  (0x7504U + (12U*(n)))

#define BM_XTAL_CTL_LP_DBG_EN  ((uint32)0x01U << 16U)

#define BM_XTAL_CTL_IGNORE_XTAL  ((uint32)0x01U << 3U)

#define BM_XTAL_CTL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_XTAL_CTL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_XTAL_CTL_RUN_MODE  ((uint32)0x01U << 0U)

#define XTAL_MON_CTL_OFF  (0x7508U)

#define BM_XTAL_MON_CTL_XTAL_CLK_ACTIVE  ((uint32)0x01U << 31U)

#define BM_XTAL_MON_CTL_RC24M_CLK_ACTIVE  ((uint32)0x01U << 30U)

#define BM_XTAL_MON_CTL_XTAL_CLK_RDY  ((uint32)0x01U << 29U)

#define BM_XTAL_MON_CTL_RC24M_CLK_RDY  ((uint32)0x01U << 28U)

#define FM_XTAL_MON_CTL_TOUT_VAL  ((uint32)0xffffU << 8U)
#define FV_XTAL_MON_CTL_TOUT_VAL(v) \
  (((uint32)(v) << 8U) & FM_XTAL_MON_CTL_TOUT_VAL)
#define GFV_XTAL_MON_CTL_TOUT_VAL(v) \
  (((uint32)(v) & FM_XTAL_MON_CTL_TOUT_VAL) >> 8U)

#define BM_XTAL_MON_CTL_MON_EN_STA  ((uint32)0x01U << 1U)

#define BM_XTAL_MON_CTL_MON_EN  ((uint32)0x01U << 0U)

#define DBG_MON_RS_OFF(n)  (0x8000U + 12U*(n))

#define BM_DBG_MON_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_DBG_MON_RS_RS  ((uint32)0xfU << 1U)
#define FV_DBG_MON_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_DBG_MON_RS_RS)
#define GFV_DBG_MON_RS_RS(v) \
  (((uint32)(v) & FM_DBG_MON_RS_RS) >> 1U)

#define BM_DBG_MON_RS_EN  ((uint32)0x01U << 0U)

#define DBG_MON_CLK_SRC_OFF  0x8004U

#define FM_DBG_MON_CLK_SRC_EXT_CLK_SRC_SEL  ((uint32)0xffU << 24U)
#define FV_DBG_MON_CLK_SRC_EXT_CLK_SRC_SEL(v) \
  (((uint32)(v) << 24U) & FM_DBG_MON_CLK_SRC_EXT_CLK_SRC_SEL)
#define GFV_DBG_MON_CLK_SRC_EXT_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_DBG_MON_CLK_SRC_EXT_CLK_SRC_SEL) >> 24U)

#define FM_DBG_MON_CLK_SRC_CORE_CLK_SRC_SEL  ((uint32)0xffU << 16U)
#define FV_DBG_MON_CLK_SRC_CORE_CLK_SRC_SEL(v) \
  (((uint32)(v) << 16U) & FM_DBG_MON_CLK_SRC_CORE_CLK_SRC_SEL)
#define GFV_DBG_MON_CLK_SRC_CORE_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_DBG_MON_CLK_SRC_CORE_CLK_SRC_SEL) >> 16U)

#define FM_DBG_MON_CLK_SRC_BUS_CLK_SRC_SEL  ((uint32)0xffU << 8U)
#define FV_DBG_MON_CLK_SRC_BUS_CLK_SRC_SEL(v) \
  (((uint32)(v) << 8U) & FM_DBG_MON_CLK_SRC_BUS_CLK_SRC_SEL)
#define GFV_DBG_MON_CLK_SRC_BUS_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_DBG_MON_CLK_SRC_BUS_CLK_SRC_SEL) >> 8U)

#define FM_DBG_MON_CLK_SRC_IP_CLK_SRC_SEL  ((uint32)0xffU << 0U)
#define FV_DBG_MON_CLK_SRC_IP_CLK_SRC_SEL(v) \
  (((uint32)(v) << 0U) & FM_DBG_MON_CLK_SRC_IP_CLK_SRC_SEL)
#define GFV_DBG_MON_CLK_SRC_IP_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_DBG_MON_CLK_SRC_IP_CLK_SRC_SEL) >> 0U)

#define DBG_MON_CTL_OFF  0x8008U

#define FM_DBG_MON_CTL_CLK_SEL  ((uint32)0x3U << 3U)
#define FV_DBG_MON_CTL_CLK_SEL(v) \
  (((uint32)(v) << 3U) & FM_DBG_MON_CTL_CLK_SEL)
#define GFV_DBG_MON_CTL_CLK_SEL(v) \
  (((uint32)(v) & FM_DBG_MON_CTL_CLK_SEL) >> 3U)

#define BM_DBG_MON_CTL_CQM_GATING_EN  ((uint32)0x01U << 2U)

#define BM_DBG_MON_CTL_MON_GATING_EN  ((uint32)0x01U << 1U)

#define BM_DBG_MON_CTL_DBG_GATING_EN  ((uint32)0x01U << 0U)

#define DBG_CTL_OFF  0x800cU

#define FM_DBG_CTL_DIV_NUM  ((uint32)0xfU << 0U)
#define FV_DBG_CTL_DIV_NUM(v) \
  (((uint32)(v) << 0U) & FM_DBG_CTL_DIV_NUM)
#define GFV_DBG_CTL_DIV_NUM(v) \
  (((uint32)(v) & FM_DBG_CTL_DIV_NUM) >> 0U)

#define MON_CTL_OFF  0x8010U

#define FM_MON_CTL_FREQ_MON  ((uint32)0xffffU << 16U)
#define FV_MON_CTL_FREQ_MON(v) \
  (((uint32)(v) << 16U) & FM_MON_CTL_FREQ_MON)
#define GFV_MON_CTL_FREQ_MON(v) \
  (((uint32)(v) & FM_MON_CTL_FREQ_MON) >> 16U)

#define BM_MON_CTL_MON_EN_STA  ((uint32)0x01U << 9U)

#define BM_MON_CTL_FREQ_MON_UPD  ((uint32)0x01U << 8U)

#define BM_MON_CTL_ACTIVE_LOSS_DIS  ((uint32)0x01U << 2U)

#define BM_MON_CTL_MON_CLK_SRC_SEL  ((uint32)0x01U << 1U)

#define BM_MON_CTL_MON_EN  ((uint32)0x01U << 0U)

#define MON_CHK_THRD_OFF  0x8014U

#define FM_MON_CHK_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_MON_CHK_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_MON_CHK_THRD_HIGH)
#define GFV_MON_CHK_THRD_HIGH(v) \
  (((uint32)(v) & FM_MON_CHK_THRD_HIGH) >> 16U)

#define FM_MON_CHK_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_MON_CHK_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_MON_CHK_THRD_LOW)
#define GFV_MON_CHK_THRD_LOW(v) \
  (((uint32)(v) & FM_MON_CHK_THRD_LOW) >> 0U)

#define LOW_SPD_CHK_CTL_OFF  0x8020U

#define FM_LOW_SPD_CHK_CTL_FREQ_MON  ((uint32)0xffffU << 16U)
#define FV_LOW_SPD_CHK_CTL_FREQ_MON(v) \
  (((uint32)(v) << 16U) & FM_LOW_SPD_CHK_CTL_FREQ_MON)
#define GFV_LOW_SPD_CHK_CTL_FREQ_MON(v) \
  (((uint32)(v) & FM_LOW_SPD_CHK_CTL_FREQ_MON) >> 16U)

#define BM_LOW_SPD_CHK_CTL_MON_EN_STA  ((uint32)0x01U << 15U)

#define BM_LOW_SPD_CHK_CTL_FREQ_MON_UPD  ((uint32)0x01U << 14U)

#define FM_LOW_SPD_CHK_CTL_32K_SRC_SEL  ((uint32)0x3fU << 8U)
#define FV_LOW_SPD_CHK_CTL_32K_SRC_SEL(v) \
  (((uint32)(v) << 8U) & FM_LOW_SPD_CHK_CTL_32K_SRC_SEL)
#define GFV_LOW_SPD_CHK_CTL_32K_SRC_SEL(v) \
  (((uint32)(v) & FM_LOW_SPD_CHK_CTL_32K_SRC_SEL) >> 8U)

#define FM_LOW_SPD_CHK_CTL_24M_SRC_SEL  ((uint32)0x3fU << 2U)
#define FV_LOW_SPD_CHK_CTL_24M_SRC_SEL(v) \
  (((uint32)(v) << 2U) & FM_LOW_SPD_CHK_CTL_24M_SRC_SEL)
#define GFV_LOW_SPD_CHK_CTL_24M_SRC_SEL(v) \
  (((uint32)(v) & FM_LOW_SPD_CHK_CTL_24M_SRC_SEL) >> 2U)

#define BM_LOW_SPD_CHK_CTL_MON_EN  ((uint32)0x01U << 1U)

#define BM_LOW_SPD_CHK_CTL_CLK_LOSS_DIS  ((uint32)0x01U << 0U)

#define LOW_SPD_CHK_THRD_OFF  0x8024U

#define FM_LOW_SPD_CHK_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_LOW_SPD_CHK_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_LOW_SPD_CHK_THRD_HIGH)
#define GFV_LOW_SPD_CHK_THRD_HIGH(v) \
  (((uint32)(v) & FM_LOW_SPD_CHK_THRD_HIGH) >> 16U)

#define FM_LOW_SPD_CHK_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_LOW_SPD_CHK_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_LOW_SPD_CHK_THRD_LOW)
#define GFV_LOW_SPD_CHK_THRD_LOW(v) \
  (((uint32)(v) & FM_LOW_SPD_CHK_THRD_LOW) >> 0U)

#define EXT_CLK_MON_CTL0_OFF  0x8030U

#define FM_EXT_CLK_MON_CTL0_FREQ_MON  ((uint32)0xffffU << 16U)
#define FV_EXT_CLK_MON_CTL0_FREQ_MON(v) \
  (((uint32)(v) << 16U) & FM_EXT_CLK_MON_CTL0_FREQ_MON)
#define GFV_EXT_CLK_MON_CTL0_FREQ_MON(v) \
  (((uint32)(v) & FM_EXT_CLK_MON_CTL0_FREQ_MON) >> 16U)

#define FM_EXT_CLK_MON_CTL0_EXT_CLK_SRC_SEL  ((uint32)0xfU << 12U)
#define FV_EXT_CLK_MON_CTL0_EXT_CLK_SRC_SEL(v) \
  (((uint32)(v) << 12U) & FM_EXT_CLK_MON_CTL0_EXT_CLK_SRC_SEL)
#define GFV_EXT_CLK_MON_CTL0_EXT_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_EXT_CLK_MON_CTL0_EXT_CLK_SRC_SEL) >> 12U)

#define BM_EXT_CLK_MON_CTL0_MON_GATING_EN  ((uint32)0x01U << 11U)

#define BM_EXT_CLK_MON_CTL0_DBG_GATING_EN  ((uint32)0x01U << 10U)

#define BM_EXT_CLK_MON_CTL0_MON_EN_STA  ((uint32)0x01U << 9U)

#define BM_EXT_CLK_MON_CTL0_FREQ_MON_UPD  ((uint32)0x01U << 8U)

#define FM_EXT_CLK_MON_CTL0_DIV_NUM  ((uint32)0xfU << 4U)
#define FV_EXT_CLK_MON_CTL0_DIV_NUM(v) \
  (((uint32)(v) << 4U) & FM_EXT_CLK_MON_CTL0_DIV_NUM)
#define GFV_EXT_CLK_MON_CTL0_DIV_NUM(v) \
  (((uint32)(v) & FM_EXT_CLK_MON_CTL0_DIV_NUM) >> 4U)

#define BM_EXT_CLK_MON_CTL0_ACTIVE_LOSS  ((uint32)0x01U << 3U)

#define BM_EXT_CLK_MON_CTL0_ACTIVE_LOSS_DIS  ((uint32)0x01U << 2U)

#define BM_EXT_CLK_MON_CTL0_MON_CLK_SRC_SEL  ((uint32)0x01U << 1U)

#define BM_EXT_CLK_MON_CTL0_MON_EN  ((uint32)0x01U << 0U)

#define EXT_CLK_MON_CTL1_OFF  0x8034U

#define FM_EXT_CLK_MON_CTL1_FREQ_MON  ((uint32)0xffffU << 16U)
#define FV_EXT_CLK_MON_CTL1_FREQ_MON(v) \
  (((uint32)(v) << 16U) & FM_EXT_CLK_MON_CTL1_FREQ_MON)
#define GFV_EXT_CLK_MON_CTL1_FREQ_MON(v) \
  (((uint32)(v) & FM_EXT_CLK_MON_CTL1_FREQ_MON) >> 16U)

#define FM_EXT_CLK_MON_CTL1_EXT_CLK_SRC_SEL  ((uint32)0xfU << 12U)
#define FV_EXT_CLK_MON_CTL1_EXT_CLK_SRC_SEL(v) \
  (((uint32)(v) << 12U) & FM_EXT_CLK_MON_CTL1_EXT_CLK_SRC_SEL)
#define GFV_EXT_CLK_MON_CTL1_EXT_CLK_SRC_SEL(v) \
  (((uint32)(v) & FM_EXT_CLK_MON_CTL1_EXT_CLK_SRC_SEL) >> 12U)

#define BM_EXT_CLK_MON_CTL1_MON_GATING_EN  ((uint32)0x01U << 11U)

#define BM_EXT_CLK_MON_CTL1_DBG_GATING_EN  ((uint32)0x01U << 10U)

#define BM_EXT_CLK_MON_CTL1_MON_EN_STA  ((uint32)0x01U << 9U)

#define BM_EXT_CLK_MON_CTL1_FREQ_MON_UPD  ((uint32)0x01U << 8U)

#define FM_EXT_CLK_MON_CTL1_DIV_NUM  ((uint32)0xfU << 4U)
#define FV_EXT_CLK_MON_CTL1_DIV_NUM(v) \
  (((uint32)(v) << 4U) & FM_EXT_CLK_MON_CTL1_DIV_NUM)
#define GFV_EXT_CLK_MON_CTL1_DIV_NUM(v) \
  (((uint32)(v) & FM_EXT_CLK_MON_CTL1_DIV_NUM) >> 4U)

#define BM_EXT_CLK_MON_CTL1_ACTIVE_LOSS  ((uint32)0x01U << 3U)

#define BM_EXT_CLK_MON_CTL1_ACTIVE_LOSS_DIS  ((uint32)0x01U << 2U)

#define BM_EXT_CLK_MON_CTL1_MON_CLK_SRC_SEL  ((uint32)0x01U << 1U)

#define BM_EXT_CLK_MON_CTL1_MON_EN  ((uint32)0x01U << 0U)

#define EXT0_CHK_THRD_OFF  0x8038U

#define FM_EXT0_CHK_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_EXT0_CHK_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_EXT0_CHK_THRD_HIGH)
#define GFV_EXT0_CHK_THRD_HIGH(v) \
  (((uint32)(v) & FM_EXT0_CHK_THRD_HIGH) >> 16U)

#define FM_EXT0_CHK_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_EXT0_CHK_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_EXT0_CHK_THRD_LOW)
#define GFV_EXT0_CHK_THRD_LOW(v) \
  (((uint32)(v) & FM_EXT0_CHK_THRD_LOW) >> 0U)

#define EXT1_CHK_THRD_OFF  0x803cU

#define FM_EXT1_CHK_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_EXT1_CHK_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_EXT1_CHK_THRD_HIGH)
#define GFV_EXT1_CHK_THRD_HIGH(v) \
  (((uint32)(v) & FM_EXT1_CHK_THRD_HIGH) >> 16U)

#define FM_EXT1_CHK_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_EXT1_CHK_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_EXT1_CHK_THRD_LOW)
#define GFV_EXT1_CHK_THRD_LOW(v) \
  (((uint32)(v) & FM_EXT1_CHK_THRD_LOW) >> 0U)

#define CQM_CTL_OFF(n)  (0x8040U + (4U*(n)))

#define FM_CQM_CTL_DUTY_RATE  ((uint32)0x3fU << 9U)
#define FV_CQM_CTL_DUTY_RATE(v) \
  (((uint32)(v) << 9U) & FM_CQM_CTL_DUTY_RATE)
#define GFV_CQM_CTL_DUTY_RATE(v) \
  (((uint32)(v) & FM_CQM_CTL_DUTY_RATE) >> 9U)

#define FM_CQM_CTL_JITTER_RATE  ((uint32)0x3fU << 3U)
#define FV_CQM_CTL_JITTER_RATE(v) \
  (((uint32)(v) << 3U) & FM_CQM_CTL_JITTER_RATE)
#define GFV_CQM_CTL_JITTER_RATE(v) \
  (((uint32)(v) & FM_CQM_CTL_JITTER_RATE) >> 3U)

#define FM_CQM_CTL_SRC_SEL  ((uint32)0x3U << 1U)
#define FV_CQM_CTL_SRC_SEL(v) \
  (((uint32)(v) << 1U) & FM_CQM_CTL_SRC_SEL)
#define GFV_CQM_CTL_SRC_SEL(v) \
  (((uint32)(v) & FM_CQM_CTL_SRC_SEL) >> 1U)

#define BM_CQM_CTL_MON_EN  ((uint32)0x01U << 0U)

#define CKGEN_FUSA_RS_OFF  0xa000U

#define BM_CKGEN_FUSA_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CKGEN_FUSA_RS_RS  ((uint32)0xfU << 1U)
#define FV_CKGEN_FUSA_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CKGEN_FUSA_RS_RS)
#define GFV_CKGEN_FUSA_RS_RS(v) \
  (((uint32)(v) & FM_CKGEN_FUSA_RS_RS) >> 1U)

#define BM_CKGEN_FUSA_RS_EN  ((uint32)0x01U << 0U)

#define APB_ERR_INT_OFF  0xa004U

#define BM_APB_ERR_INT_PADDR_INT_CLR  ((uint32)0x01U << 23U)

#define BM_APB_ERR_INT_PUSER_INT_CLR  ((uint32)0x01U << 22U)

#define BM_APB_ERR_INT_PCTRL1_INT_CLR  ((uint32)0x01U << 21U)

#define BM_APB_ERR_INT_PCTRL0_INT_CLR  ((uint32)0x01U << 20U)

#define BM_APB_ERR_INT_PWDAT_C_INT_CLR  ((uint32)0x01U << 19U)

#define BM_APB_ERR_INT_PWDAT_U_INT_CLR  ((uint32)0x01U << 18U)

#define BM_APB_ERR_INT_PWDAT_F_INT_CLR  ((uint32)0x01U << 17U)

#define BM_APB_ERR_INT_PADDR_INT_STA  ((uint32)0x01U << 15U)

#define BM_APB_ERR_INT_PUSER_INT_STA  ((uint32)0x01U << 14U)

#define BM_APB_ERR_INT_PCTRL1_INT_STA  ((uint32)0x01U << 13U)

#define BM_APB_ERR_INT_PCTRL0_INT_STA  ((uint32)0x01U << 12U)

#define BM_APB_ERR_INT_PWDAT_C_INT_STA  ((uint32)0x01U << 11U)

#define BM_APB_ERR_INT_PWDAT_U_INT_STA  ((uint32)0x01U << 10U)

#define BM_APB_ERR_INT_PWDAT_F_INT_STA  ((uint32)0x01U << 9U)

#define BM_APB_ERR_INT_PADDR_INT_EN  ((uint32)0x01U << 7U)

#define BM_APB_ERR_INT_PUSER_INT_EN  ((uint32)0x01U << 6U)

#define BM_APB_ERR_INT_PCTRL1_INT_EN  ((uint32)0x01U << 5U)

#define BM_APB_ERR_INT_PCTRL0_INT_EN  ((uint32)0x01U << 4U)

#define BM_APB_ERR_INT_PWDAT_C_INT_EN  ((uint32)0x01U << 3U)

#define BM_APB_ERR_INT_PWDAT_U_INT_EN  ((uint32)0x01U << 2U)

#define BM_APB_ERR_INT_PWDAT_F_INT_EN  ((uint32)0x01U << 1U)

#define WDT_LKSTEP_INT_OFF  0xa00cU

#define BM_WDT_LKSTEP_INT_SYNC_ERR_INT_CLR  ((uint32)0x01U << 17U)

#define BM_WDT_LKSTEP_INT_SYNC_ERR_INT_STA  ((uint32)0x01U << 9U)

#define BM_WDT_LKSTEP_INT_SYNC_ERR_INT_EN  ((uint32)0x01U << 1U)

#define CKGEN_FUSA_INT_OFF  0xa100U

#define BM_CKGEN_FUSA_INT_SWM_ACK_HIB_ERR_CLR  ((uint32)0x01U << 21U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_SLP_ERR_CLR  ((uint32)0x01U << 20U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_RUN_ERR_CLR  ((uint32)0x01U << 19U)

#define BM_CKGEN_FUSA_INT_SYNC_ERR_CLR  ((uint32)0x01U << 18U)

#define BM_CKGEN_FUSA_INT_SWM_TRANS_ERR_CLR  ((uint32)0x01U << 17U)

#define BM_CKGEN_FUSA_INT_SWM_CHK_ERR_CLR  ((uint32)0x01U << 16U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_HIB_ERR_STA  ((uint32)0x01U << 13U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_SLP_ERR_STA  ((uint32)0x01U << 12U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_RUN_ERR_STA  ((uint32)0x01U << 11U)

#define BM_CKGEN_FUSA_INT_SYNC_ERR_STA  ((uint32)0x01U << 10U)

#define BM_CKGEN_FUSA_INT_SWM_TRANS_ERR_STA  ((uint32)0x01U << 9U)

#define BM_CKGEN_FUSA_INT_SWM_CHK_ERR_STA  ((uint32)0x01U << 8U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_HIB_ERR_EN  ((uint32)0x01U << 5U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_SLP_ERR_EN  ((uint32)0x01U << 4U)

#define BM_CKGEN_FUSA_INT_SWM_ACK_RUN_ERR_EN  ((uint32)0x01U << 3U)

#define BM_CKGEN_FUSA_INT_SYNC_ERR_EN  ((uint32)0x01U << 2U)

#define BM_CKGEN_FUSA_INT_SWM_TRANS_ERR_EN  ((uint32)0x01U << 1U)

#define BM_CKGEN_FUSA_INT_SWM_CHK_ERR_EN  ((uint32)0x01U << 0U)

#define CKGEN_WDAT_ERR_INJ_OFF  0xa200U

#define FM_WDAT_ERR_INJ_ERR_INJ  ((uint32)0xffffffffU << 0U)
#define FV_WDAT_ERR_INJ_ERR_INJ(v) \
  (((uint32)(v) << 0U) & FM_WDAT_ERR_INJ_ERR_INJ)
#define GFV_WDAT_ERR_INJ_ERR_INJ(v) \
  (((uint32)(v) & FM_WDAT_ERR_INJ_ERR_INJ) >> 0U)

#define CKGEN_WECC_ERR_INJ_OFF  0xa204U

#define FM_WECC_ERR_INJ_ERR_INJ  ((uint32)0x7fU << 0U)
#define FV_WECC_ERR_INJ_ERR_INJ(v) \
  (((uint32)(v) << 0U) & FM_WECC_ERR_INJ_ERR_INJ)
#define GFV_WECC_ERR_INJ_ERR_INJ(v) \
  (((uint32)(v) & FM_WECC_ERR_INJ_ERR_INJ) >> 0U)

#define CKGEN_PRDATAINJ_OFF  0xa208U

#define CKGEN_REG_PARITY_ERR_INT_STAT_OFF  0xa20cU

#define CKGEN_REG_PARITY_ERR_INT_SIG_EN_OFF  0xa210U

#define ERR_INJ_EN_OFF  0xa214U

#define BM_ERR_INJ_EN_TOUT_ERR_INJ_EN  ((uint32)0x01U << 4U)

#define BM_ERR_INJ_EN_WDT_ERR_INJ_EN  ((uint32)0x01U << 3U)

#define BM_ERR_INJ_EN_OUT_ERR_INJ_EN  ((uint32)0x01U << 2U)

#define BM_ERR_INJ_EN_IRQ_ERR_INJ_EN  ((uint32)0x01U << 1U)

#define BM_ERR_INJ_EN_APB_ERR_INJ_EN  ((uint32)0x01U << 0U)

#define ERR_INJ_BIT_OFF  0xa218U

#define FM_ERR_INJ_BIT_ERR_INJ_BIT  ((uint32)0xffffU << 16U)
#define FV_ERR_INJ_BIT_ERR_INJ_BIT(v) \
  (((uint32)(v) << 16U) & FM_ERR_INJ_BIT_ERR_INJ_BIT)
#define GFV_ERR_INJ_BIT_ERR_INJ_BIT(v) \
  (((uint32)(v) & FM_ERR_INJ_BIT_ERR_INJ_BIT) >> 16U)

#define BM_ERR_INJ_BIT_UNC_IRQ  ((uint32)0x01U << 2U)

#define BM_ERR_INJ_BIT_COR_IRQ  ((uint32)0x01U << 1U)

#define BM_ERR_INJ_BIT_FUNC_IRQ  ((uint32)0x01U << 0U)

#define SELFTEST_MODE_OFF  0xa21cU

#define IP_CLK_COR_EN_OFF(n)  (0xa300U + (12U*(n)))

#define FM_IP_CLK_COR_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_IP_CLK_COR_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_IP_CLK_COR_EN_INT_EN)
#define GFV_IP_CLK_COR_EN_INT_EN(v) \
  (((uint32)(v) & FM_IP_CLK_COR_EN_INT_EN) >> 0U)

#define IP_CLK_UNC_EN_OFF(n)  (0xa304U + (12U*(n)))

#define FM_IP_CLK_UNC_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_IP_CLK_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_IP_CLK_UNC_EN_INT_EN)
#define GFV_IP_CLK_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_IP_CLK_UNC_EN_INT_EN) >> 0U)

#define IP_CLK_INT_STA_OFF(n)  (0xa308U + (12U*(n)))

#define BM_IP_CLK_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_IP_CLK_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_IP_CLK_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_IP_CLK_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_IP_CLK_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_IP_CLK_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_IP_CLK_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_IP_CLK_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_IP_CLK_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_IP_CLK_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_IP_CLK_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_IP_CLK_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_IP_CLK_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_IP_CLK_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_IP_CLK_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_IP_CLK_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_IP_CLK_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_IP_CLK_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_IP_CLK_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_IP_CLK_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_IP_CLK_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_IP_CLK_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_IP_CLK_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_IP_CLK_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_IP_CLK_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_IP_CLK_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_IP_CLK_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_IP_CLK_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_IP_CLK_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_IP_CLK_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_IP_CLK_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_IP_CLK_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define BUS_CLK_COR_EN_OFF  (0xa400U)

#define FM_BUS_CLK_COR_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_BUS_CLK_COR_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_BUS_CLK_COR_EN_INT_EN)
#define GFV_BUS_CLK_COR_EN_INT_EN(v) \
  (((uint32)(v) & FM_BUS_CLK_COR_EN_INT_EN) >> 0U)

#define BUS_CLK_UNC_EN_OFF  (0xa404U)

#define FM_BUS_CLK_UNC_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_BUS_CLK_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_BUS_CLK_UNC_EN_INT_EN)
#define GFV_BUS_CLK_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_BUS_CLK_UNC_EN_INT_EN) >> 0U)

#define BUS_CLK_INT_STA_OFF  (0xa408U)

#define BM_BUS_CLK_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_BUS_CLK_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_BUS_CLK_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_BUS_CLK_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_BUS_CLK_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_BUS_CLK_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_BUS_CLK_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_BUS_CLK_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_BUS_CLK_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_BUS_CLK_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_BUS_CLK_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_BUS_CLK_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_BUS_CLK_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_BUS_CLK_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_BUS_CLK_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_BUS_CLK_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_BUS_CLK_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_BUS_CLK_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_BUS_CLK_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_BUS_CLK_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_BUS_CLK_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_BUS_CLK_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_BUS_CLK_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_BUS_CLK_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_BUS_CLK_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_BUS_CLK_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_BUS_CLK_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_BUS_CLK_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_BUS_CLK_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_BUS_CLK_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_BUS_CLK_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_BUS_CLK_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define CORE_CLK_COR_EN_OFF(n)  (0xa500U + 12U*(n))

#define FM_CORE_CLK_COR_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_CORE_CLK_COR_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_CORE_CLK_COR_EN_INT_EN)
#define GFV_CORE_CLK_COR_EN_INT_EN(v) \
  (((uint32)(v) & FM_CORE_CLK_COR_EN_INT_EN) >> 0U)

#define CORE_CLK_UNC_EN_OFF(n)  (0xa504U + 12U*(n))

#define FM_CORE_CLK_UNC_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_CORE_CLK_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_CORE_CLK_UNC_EN_INT_EN)
#define GFV_CORE_CLK_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_CORE_CLK_UNC_EN_INT_EN) >> 0U)

#define CORE_CLK_INT_STA_OFF(n)  (0xa508U + (12U*(n)))

#define BM_CORE_CLK_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_CORE_CLK_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_CORE_CLK_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_CORE_CLK_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_CORE_CLK_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_CORE_CLK_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_CORE_CLK_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_CORE_CLK_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_CORE_CLK_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_CORE_CLK_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_CORE_CLK_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_CORE_CLK_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_CORE_CLK_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_CORE_CLK_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_CORE_CLK_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_CORE_CLK_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_CORE_CLK_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_CORE_CLK_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_CORE_CLK_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_CORE_CLK_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_CORE_CLK_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_CORE_CLK_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_CORE_CLK_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_CORE_CLK_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_CORE_CLK_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_CORE_CLK_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_CORE_CLK_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_CORE_CLK_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_CORE_CLK_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_CORE_CLK_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_CORE_CLK_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_CORE_CLK_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define PCG_COR_EN_OFF(n)  (0xa600U + (12U*(n)))

#define FM_PCG_COR_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_PCG_COR_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_PCG_COR_EN_INT_EN)
#define GFV_PCG_COR_EN_INT_EN(v) \
  (((uint32)(v) & FM_PCG_COR_EN_INT_EN) >> 0U)

#define PCG_UNC_EN_OFF(n)  (0xa604U + (12U*(n)))

#define FM_PCG_UNC_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_PCG_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_PCG_UNC_EN_INT_EN)
#define GFV_PCG_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_PCG_UNC_EN_INT_EN) >> 0U)

#define PCG_INT_STA_OFF(n)  (0xa608U + (12U*(n)))

#define BM_PCG_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_PCG_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_PCG_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_PCG_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_PCG_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_PCG_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_PCG_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_PCG_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_PCG_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_PCG_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_PCG_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_PCG_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_PCG_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_PCG_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_PCG_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_PCG_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_PCG_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_PCG_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_PCG_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_PCG_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_PCG_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_PCG_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_PCG_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_PCG_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_PCG_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_PCG_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_PCG_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_PCG_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_PCG_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_PCG_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_PCG_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_PCG_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define BCG_COR_EN_OFF(n)  (0xa700U + (12U*(n)))

#define FM_BCG_COR_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_BCG_COR_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_BCG_COR_EN_INT_EN)
#define GFV_BCG_COR_EN_INT_EN(v) \
  (((uint32)(v) & FM_BCG_COR_EN_INT_EN) >> 0U)

#define BCG_UNC_EN_OFF(n)  (0xa704U + (12U*(n)))

#define FM_BCG_UNC_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_BCG_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_BCG_UNC_EN_INT_EN)
#define GFV_BCG_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_BCG_UNC_EN_INT_EN) >> 0U)

#define BCG_INT_STA_OFF(n)  (0xa708U + (12U*(n)))

#define BM_BCG_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_BCG_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_BCG_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_BCG_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_BCG_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_BCG_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_BCG_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_BCG_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_BCG_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_BCG_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_BCG_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_BCG_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_BCG_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_BCG_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_BCG_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_BCG_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_BCG_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_BCG_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_BCG_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_BCG_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_BCG_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_BCG_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_BCG_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_BCG_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_BCG_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_BCG_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_BCG_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_BCG_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_BCG_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_BCG_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_BCG_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_BCG_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define CCG_COR_EN_OFF(n)  (0xa800U + 12U*(n))

#define FM_CCG_COR_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_CCG_COR_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_CCG_COR_EN_INT_EN)
#define GFV_CCG_COR_EN_INT_EN(v) \
  (((uint32)(v) & FM_CCG_COR_EN_INT_EN) >> 0U)

#define CCG_UNC_EN_OFF(n)  (0xa804U + 12U*(n))

#define FM_CCG_UNC_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_CCG_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_CCG_UNC_EN_INT_EN)
#define GFV_CCG_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_CCG_UNC_EN_INT_EN) >> 0U)

#define CCG_INT_STA_OFF(n)  (0xa808U + 12U*(n))

#define BM_CCG_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_CCG_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_CCG_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_CCG_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_CCG_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_CCG_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_CCG_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_CCG_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_CCG_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_CCG_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_CCG_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_CCG_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_CCG_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_CCG_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_CCG_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_CCG_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_CCG_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_CCG_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_CCG_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_CCG_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_CCG_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_CCG_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_CCG_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_CCG_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_CCG_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_CCG_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_CCG_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_CCG_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_CCG_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_CCG_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_CCG_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_CCG_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define PLL_UNC_EN_OFF  0xa904U

#define FM_PLL_UNC_EN_INT_EN  ((uint32)0xffU << 0U)
#define FV_PLL_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_PLL_UNC_EN_INT_EN)
#define GFV_PLL_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_PLL_UNC_EN_INT_EN) >> 0U)

#define PLL_INT_STA_OFF  0xa908U

#define BM_PLL_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_PLL_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_PLL_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define XTAL_UNC_EN_OFF  0xaa04U

#define FM_XTAL_UNC_EN_INT_EN  ((uint32)0xffU << 0U)
#define FV_XTAL_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_XTAL_UNC_EN_INT_EN)
#define GFV_XTAL_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_XTAL_UNC_EN_INT_EN) >> 0U)

#define XTAL_INT_STA_OFF  0xaa08U

#define BM_XTAL_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define MON_COR_EN_OFF  0xab00U

#define BM_MON_COR_EN_INT_EN  ((uint32)0x01U << 0U)

#define MON_UNC_EN_OFF  0xab04U

#define BM_MON_UNC_EN_INT_EN  ((uint32)0x01U << 0U)

#define MON_INT_STA_OFF  0xab08U

#define BM_MON_INT_STA_INT_STA  ((uint32)0x01U << 0U)

#define LOW_SPD_COR_EN_OFF  0xac00U

#define BM_LOW_SPD_COR_EN_INT_EN_2  ((uint32)0x01U << 2U)

#define BM_LOW_SPD_COR_EN_INT_EN_1  ((uint32)0x01U << 1U)

#define BM_LOW_SPD_COR_EN_INT_EN  ((uint32)0x01U << 0U)

#define LOW_SPD_UNC_EN_OFF  0xac04U

#define BM_LOW_SPD_UNC_EN_INT_EN_2  ((uint32)0x01U << 2U)

#define BM_LOW_SPD_UNC_EN_INT_EN_1  ((uint32)0x01U << 1U)

#define BM_LOW_SPD_UNC_EN_INT_EN  ((uint32)0x01U << 0U)

#define LOW_SPD_INT_STA_OFF  0xac08U

#define BM_LOW_SPD_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_LOW_SPD_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_LOW_SPD_INT_STA_INT_STA  ((uint32)0x01U << 0U)

#define CQM_COR_EN_OFF  0xad00U

#define FM_CQM_COR_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_CQM_COR_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_CQM_COR_EN_INT_EN)
#define GFV_CQM_COR_EN_INT_EN(v) \
  (((uint32)(v) & FM_CQM_COR_EN_INT_EN) >> 0U)

#define CQM_UNC_EN_OFF  0xad04U

#define FM_CQM_UNC_EN_INT_EN  ((uint32)0xffffffffU << 0U)
#define FV_CQM_UNC_EN_INT_EN(v) \
  (((uint32)(v) << 0U) & FM_CQM_UNC_EN_INT_EN)
#define GFV_CQM_UNC_EN_INT_EN(v) \
  (((uint32)(v) & FM_CQM_UNC_EN_INT_EN) >> 0U)

#define CQM_DUTY_INT_STA_OFF  0xad08U

#define BM_CQM_DUTY_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_CQM_DUTY_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_CQM_DUTY_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_CQM_DUTY_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_CQM_DUTY_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_CQM_DUTY_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_CQM_DUTY_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_CQM_DUTY_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_CQM_DUTY_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_CQM_DUTY_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_CQM_DUTY_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_CQM_DUTY_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_CQM_DUTY_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_CQM_DUTY_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_CQM_DUTY_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_CQM_DUTY_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_CQM_DUTY_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_CQM_DUTY_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_CQM_DUTY_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_CQM_DUTY_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_CQM_DUTY_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_CQM_DUTY_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_CQM_DUTY_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_CQM_DUTY_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_CQM_DUTY_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_CQM_DUTY_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_CQM_DUTY_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_CQM_DUTY_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_CQM_DUTY_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_CQM_DUTY_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_CQM_DUTY_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_CQM_DUTY_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define CQM_JITTER_INT_STA_OFF  0xad0cU

#define BM_CQM_JITTER_INT_STA_INT_STA_31  ((uint32)0x01U << 31U)

#define BM_CQM_JITTER_INT_STA_INT_STA_30  ((uint32)0x01U << 30U)

#define BM_CQM_JITTER_INT_STA_INT_STA_29  ((uint32)0x01U << 29U)

#define BM_CQM_JITTER_INT_STA_INT_STA_28  ((uint32)0x01U << 28U)

#define BM_CQM_JITTER_INT_STA_INT_STA_27  ((uint32)0x01U << 27U)

#define BM_CQM_JITTER_INT_STA_INT_STA_26  ((uint32)0x01U << 26U)

#define BM_CQM_JITTER_INT_STA_INT_STA_25  ((uint32)0x01U << 25U)

#define BM_CQM_JITTER_INT_STA_INT_STA_24  ((uint32)0x01U << 24U)

#define BM_CQM_JITTER_INT_STA_INT_STA_23  ((uint32)0x01U << 23U)

#define BM_CQM_JITTER_INT_STA_INT_STA_22  ((uint32)0x01U << 22U)

#define BM_CQM_JITTER_INT_STA_INT_STA_21  ((uint32)0x01U << 21U)

#define BM_CQM_JITTER_INT_STA_INT_STA_20  ((uint32)0x01U << 20U)

#define BM_CQM_JITTER_INT_STA_INT_STA_19  ((uint32)0x01U << 19U)

#define BM_CQM_JITTER_INT_STA_INT_STA_18  ((uint32)0x01U << 18U)

#define BM_CQM_JITTER_INT_STA_INT_STA_17  ((uint32)0x01U << 17U)

#define BM_CQM_JITTER_INT_STA_INT_STA_16  ((uint32)0x01U << 16U)

#define BM_CQM_JITTER_INT_STA_INT_STA_15  ((uint32)0x01U << 15U)

#define BM_CQM_JITTER_INT_STA_INT_STA_14  ((uint32)0x01U << 14U)

#define BM_CQM_JITTER_INT_STA_INT_STA_13  ((uint32)0x01U << 13U)

#define BM_CQM_JITTER_INT_STA_INT_STA_12  ((uint32)0x01U << 12U)

#define BM_CQM_JITTER_INT_STA_INT_STA_11  ((uint32)0x01U << 11U)

#define BM_CQM_JITTER_INT_STA_INT_STA_10  ((uint32)0x01U << 10U)

#define BM_CQM_JITTER_INT_STA_INT_STA_9  ((uint32)0x01U << 9U)

#define BM_CQM_JITTER_INT_STA_INT_STA_8  ((uint32)0x01U << 8U)

#define BM_CQM_JITTER_INT_STA_INT_STA_7  ((uint32)0x01U << 7U)

#define BM_CQM_JITTER_INT_STA_INT_STA_6  ((uint32)0x01U << 6U)

#define BM_CQM_JITTER_INT_STA_INT_STA_5  ((uint32)0x01U << 5U)

#define BM_CQM_JITTER_INT_STA_INT_STA_4  ((uint32)0x01U << 4U)

#define BM_CQM_JITTER_INT_STA_INT_STA_3  ((uint32)0x01U << 3U)

#define BM_CQM_JITTER_INT_STA_INT_STA_2  ((uint32)0x01U << 2U)

#define BM_CQM_JITTER_INT_STA_INT_STA_1  ((uint32)0x01U << 1U)

#define BM_CQM_JITTER_INT_STA_INT_STA_0  ((uint32)0x01U << 0U)

#define CQM_DBG_STA_OFF  0xad20U

#define FM_CQM_DBG_STA_DBG_STA  ((uint32)0xfffffffU << 4U)
#define FV_CQM_DBG_STA_DBG_STA(v) \
  (((uint32)(v) << 4U) & FM_CQM_DBG_STA_DBG_STA)
#define GFV_CQM_DBG_STA_DBG_STA(v) \
  (((uint32)(v) & FM_CQM_DBG_STA_DBG_STA) >> 4U)

#define FM_CQM_DBG_STA_DBG_SEL  ((uint32)0xfU << 0U)
#define FV_CQM_DBG_STA_DBG_SEL(v) \
  (((uint32)(v) << 0U) & FM_CQM_DBG_STA_DBG_SEL)
#define GFV_CQM_DBG_STA_DBG_SEL(v) \
  (((uint32)(v) & FM_CQM_DBG_STA_DBG_SEL) >> 0U)

#define CKGEN_FUNC_INT_RS_OFF  0xb000U

#define BM_CKGEN_FUNC_INT_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CKGEN_FUNC_INT_RS_RS  ((uint32)0xfU << 1U)
#define FV_CKGEN_FUNC_INT_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CKGEN_FUNC_INT_RS_RS)
#define GFV_CKGEN_FUNC_INT_RS_RS(v) \
  (((uint32)(v) & FM_CKGEN_FUNC_INT_RS_RS) >> 1U)

#define BM_CKGEN_FUNC_INT_RS_EN  ((uint32)0x01U << 0U)

#define CKGEN_FUNC_INT_OFF  0xb004U

#define BM_CKGEN_FUNC_INT_ACCESS_PER_ERR_CLR  ((uint32)0x01U << 16U)

#define BM_CKGEN_FUNC_INT_ACCESS_PER_ERR_STA  ((uint32)0x01U << 8U)

#define BM_CKGEN_FUNC_INT_ACCESS_PER_ERR_EN  ((uint32)0x01U << 0U)

/* BUS index */
#define CKGEN_BUS_ID_TYPE_ROOT              (0U)
#define CKGEN_BUS_ID_TYPE_DIV_ROOT          (1U)
#define CKGEN_BUS_ID_TYPE_DIV_M             (2U)
#define CKGEN_BUS_ID_TYPE_DIV_N             (3U)
#define CKGEN_BUS_ID_TYPE_DIV_P             (4U)
#define CKGEN_BUS_ID_TYPE_DIV_Q             (5U)
#define CKGEN_BUS_ID_TYPE_DIV_SF            (6U)
#define CKGEN_BUS_ID_TYPE_DIV_SP            (7U)
#define CKGEN_BUS_ID_TYPE_LSB               (24U)
#define CKGEN_BUS_ID_TYPE_MASK              (0xFFU)
#define CKGEN_BUS_ID_NUM_LSB                (0U)
#define CKGEN_BUS_ID_NUM_MASK               (0xFFFFU)

/* CG type */
#define CKGEN_CG_ID_TYPE_PCG_TYPE           (0U)
#define CKGEN_CG_ID_TYPE_BCG_TYPE           (1U)
#define CKGEN_CG_ID_TYPE_CCG_TYPE           (2U)
#define CKGEN_CG_ID_TYPE_PLL_TYPE           (3U)
#define CKGEN_CG_ID_TYPE_XTAL_TYPE          (4U)
#define CKGEN_CG_ID_TYPE_LSB                (24U)
#define CKGEN_CG_ID_TYPE_MASK               (0xFFU)
#define CKGEN_CG_ID_NUM_LSB                 (0U)
#define CKGEN_CG_ID_NUM_MASK                (0xFFFFU)

/* Ckgen monitor div type */
#define CKGEN_MON_DIVA                      (0U)
#define CKGEN_MON_DIVB                      (1U)
#define CKGEN_MON_DIVC                      (2U)

#define CKGEN_XCG_CTL_BASE(base, id, m) \
    ((base) + (PCG_CTL_OFF(id) + ((m) * 1000U)))

#define CKGEN_XCG_COR_EN_BASE(base, id, m) \
    ((base) + (PCG_COR_EN_OFF(id) + ((m) *100U)))

#define CKGEN_XCG_UNC_EN_BASE(base, id, m) \
    ((base) + (PCG_UNC_EN_OFF(id) + ((m) *100U)))

#define CKGEN_XCG_INT_STA_BASE(base, id, m) \
    ((base) + (PCG_INT_STA_OFF(id) + ((m) *100U)))


#define CKGEN_WAIT_TIME                     (30000U)

#define LOW_32K_FREQ    (32768U)
#define CKGEN_AXI_MAX_RATE                  400000000U
#define CKGEN_SLICE_PARENT(ckgen, mux)   (ckgen->parents[(mux)])
/********************************************************************************************************
 *                                  Global Types definition                                             *
 *******************************************************************************************************/
typedef uint32 Mcu_CkgenRateType;
/********************************************************************************************************
 *                                  Global FUnction Declarations                                        *
 *******************************************************************************************************/
/** *****************************************************************************************************
 * \brief bus slice ratio get
 *
 * \verbatim
 * Syntax             : static Mcu_CkgenRateType Mcu_Ip_CkgenBusGetRatio(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : ratio - 0:core/axi/apb 4/2/1, 1:core/axi/apb 2/2/1
 *
 * Description        : bus slice ratio get
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Mcu_CkgenRateType Mcu_Ip_CkgenBusGetRatio(uint32 base);

/** *****************************************************************************************************
 * \brief bus slice premux get
 *
 * \verbatim
 * Syntax             : uint8 Mcu_Ip_CkgenBusGetPreMux(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : premux
 *
 * Description        : bus slice premux get
 *
 * \endverbatim
 *******************************************************************************************************/
uint8 Mcu_Ip_CkgenBusGetPreMux(uint32 base, uint32 id);

/** *****************************************************************************************************
 * \brief bus slice divroot rate get
 *
 * \verbatim
 * Syntax             : Mcu_CkgenRateType Mcu_Ip_CkgenBusDivRootGetRate(uint32 base, uint32 id, Mcu_CkgenRateType srcRate)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - bus slice id
 *                      srcRate - parent rate
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : bus slice divroot rate
 *
 * Description        : bus slice divroot rate get
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Mcu_CkgenRateType Mcu_Ip_CkgenBusDivRootGetRate(uint32 base, uint32 id, Mcu_CkgenRateType srcRate);

/** *****************************************************************************************************
 * \brief bus slice mnpq rate get
 *
 * \verbatim
 * Syntax             : Mcu_CkgenRateType Mcu_Ip_CkgenBusDivMnpqGetRate(uint32 base, uint32 id,
                                                Mcu_CkgenRateType srcRate)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - bus slice id
 *                      srcRate - parent rate
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : bus slice mnpq rate
 *
 * Description        : bus slice mnpq rate get
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Mcu_CkgenRateType Mcu_Ip_CkgenBusDivMnpqGetRate(uint32 base, uint32 id, uint32 type,
        Mcu_CkgenRateType srcRate);

/** *****************************************************************************************************
 * \brief bus slice root set rate
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_CkgenBusRootSetRate(uint32 base, uint32 id, uint8 mux)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - bus slice id
 *                      mux - mux
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : bus slice root set rate.
 *                      mux0 - out is from m
 *                      mux1 - out is from pll
 * .
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_CkgenBusRootSetRate(uint32 base, uint32 id, uint8 mux);
/** *****************************************************************************************************
 * \brief bus slice divroot set rate
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_CkgenBusDivRootSetRate(uint32 base, Mcu_CkgenType type, uint32 id, uint8 mux, uint32 divNum)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      type - bus slice type
 *                      id - bus slice id
 *                      mux - mux
 *                      divNum - divNum
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : bus slice divroot set rate.
 *                      Preset core:axi:bus 4:2:1 to avoid freq is too high when switch to clkin4 momentary.
 *                      Preset div m/n/p to avoid freq is too high.
 *                      When switching between 0~3 and 4, ensure that both are active before switching;
 *                      When switching between 0~3, ensure that pre-en is off;
 *                      clkin4 do not have pre-div.
 * .
 * \endverbatim
 * Traceability       : SW_SM005 SW_MCU_SM012
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_CkgenBusDivRootSetRate(uint32 base, Mcu_CkgenType type, uint32 id, uint8 mux,
        uint32 divNum);
/** *****************************************************************************************************
 * \brief bus slice set rate
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_CkgenBusMnpqSetRate(uint32 base, uint32 id, Mcu_ClkBusRatioType postDiv, uint32 mDiv)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - bus slice id
 *                      postDiv - cpu:axi:apb ratio
 *                      mDiv - m div
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : bus slice set rate
 *
 * \endverbatim
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_CkgenBusMnpqSetRate(uint32 base, uint32 id, Mcu_ClkBusRatioType postDiv, uint32 mDiv);

/** *****************************************************************************************************
 * \brief ip slice mux get
 *
 * \verbatim
 * Syntax             : uint8 Mcu_Ip_CkgenIpGetMux(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - ip slice id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : mux
 *
 * Description        : ip slice mux get
 *
 * \endverbatim
 *******************************************************************************************************/
uint8 Mcu_Ip_CkgenIpGetMux(uint32 base, uint32 id);

/** *****************************************************************************************************
 * \brief ip slice div get
 *
 * \verbatim
 * Syntax             : uint32 Mcu_Ip_CkgenIpGetDiv(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - ip slice id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : div
 *
 * Description        : ip slice div get
 *
 * \endverbatim
 *******************************************************************************************************/
uint32 Mcu_Ip_CkgenIpGetDiv(uint32 base, uint32 id);

/** *****************************************************************************************************
 * \brief ip slice set rate
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_CkgenIpSetRate(uint32 base, uint32 id, uint8 mux, uint32 divNum)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - ip slice id
 *                      mux - mux
 *                      divNum - divNum
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : ip slice set rate
 *                      Preset div to avoid freq is too high when switch to clkin4 momentary.
 *                      When switching between 0~3 and 4, ensure that both are active before switching;
 *                      When switching between 0~3, ensure that pre-en is off;
 * .
 * \endverbatim
 * Traceability       : SW_MCU_SM013
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_CkgenIpSetRate(uint32 base, uint32 id, uint8 mux, uint32 divNum);

/** *****************************************************************************************************
 * \brief Clock gate turn on/off in run mode.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_CkgenXcgSetGating(uint32 base, uint32 id, uint32 type, boolean en)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - clock gate id
 *                      type - cgtype PCG 0, BCG 1, CCG 2
 *                      en - 1:on, 0:off
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : Clock gate turn on/off in run mode.
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_CkgenXcgSetGating(uint32 base, uint32 id, uint32 type, boolean en);

/** *****************************************************************************************************
 * \brief Clk check gated state.
 *
 * \verbatim
 * Syntax             : boolean Mcu_Ip_CkgenXcgIsGated(uint32 base, uint32 id, uint32 type)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - clock gate id
 *                      type - cgtype PCG 0, BCG 1, CCG 2
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : clock gate state
 *
 * Description        : get the clock gate state in run mode.
 *                      return 1 means gated, 0 means active.
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
boolean Mcu_Ip_CkgenXcgIsGated(uint32 base, uint32 id, uint32 type);

/** *****************************************************************************************************
 * \brief get interrupt status
 *
 * \verbatim
 * Syntax             : uint8 Mcu_Ip_CkgenGetIntStatus(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      sliceType - sliceType
 *                      typeIndex - typeIndex
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : get interrupt status
 * \endverbatim
 *******************************************************************************************************/
uint8 Mcu_Ip_CkgenGetIntStatus(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex);
/** *****************************************************************************************************
 * \brief clear interrupt status
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenClearIntStatus(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      sliceType - sliceType
 *                      typeIndex - typeIndex
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : clear interrupt status
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenClearIntStatus(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex);

/** *****************************************************************************************************
 * \brief get ready state
 *
 * \verbatim
 * Syntax             : uint8 Mcu_Ip_CkgenGetReadyState(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      sliceType - sliceType
 *                      typeIndex - typeIndex
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 1-ready, 0-not ready
 *
 * Description        : get ready state
 *
 * \endverbatim
 *******************************************************************************************************/
uint8 Mcu_Ip_CkgenGetReadyState(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex);
/** *****************************************************************************************************
 * \brief clear monitor threshold and interrupt status
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenSliceMonClrBusErrStatus(uint32 base, Mcu_CkgenType sliceType, uint8 typeIndex)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      sliceType - sliceType
 *                      typeIndex - typeIndex
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : clear monitor threshold and interrupt status
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenSliceMonClrBusErrStatus(uint32 base, Mcu_CkgenType sliceType, uint8 typeIndex);

/** *****************************************************************************************************
 * \brief ip slice debug sorce config.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenDbgMonIpSelect(uint32 base, uint32 id, uint8 divNum))
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - slice id
 *                      divNum - divNum
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : ip slice debug sorce config.
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
void Mcu_Ip_CkgenDbgMonIpSelect(uint32 base, uint32 id, uint8 divNum);

/** *****************************************************************************************************
 * \brief bus slice debug sorce config.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenDbgMonBusSelect(uint32 base, uint32 id, uint8 divNum))
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - slice id
 *                      divNum - divNum
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : bus slice debug sorce config.
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
void Mcu_Ip_CkgenDbgMonBusSelect(uint32 base, uint32 id, uint8 divNum);
/** *****************************************************************************************************
 * \brief ext clk debug sorce config.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenDbgMonExtSelect(uint32 base, uint32 id, uint8 divNum)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - slice id
 *                      divNum - divNum
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : ext clk debug sorce config.
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
void Mcu_Ip_CkgenDbgMonExtSelect(uint32 base, uint32 id, uint8 divNum);

/** *****************************************************************************************************
 * \brief get dbgMon interrupt status
 *
 * \verbatim
 * Syntax             : boolean Mcu_Ip_CkgenDbgMonGetIntState(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : TRUE- INTERRUPT, FALSE- NO INTERRUPT
 *
 * Description        : get dbgMon interrupt status
 * \endverbatim
 *******************************************************************************************************/
boolean Mcu_Ip_CkgenDbgMonGetIntState(uint32 base);

/** *****************************************************************************************************
 * \brief clear dbgMon interrupt status
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenDbgMonClearIntState(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : clear dbgMon interrupt status
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenDbgMonClearIntState(uint32 base);

/** *****************************************************************************************************
 * \brief dbgMon sorce config.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenDbgMonSelect(uint32 base, uint8 type, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      type - slice type
 *                      id - slice id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : dbgMon sorce config.
 *
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenDbgMonSelect(uint32 base, uint8 type, uint32 id);
/** *****************************************************************************************************
 * \brief get duty interrupt state.
 *
 * \verbatim
 * Syntax             : boolean Mcu_Ip_CkgenCqmGetDutyIntState(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : TRUE- INTERRUPT, FALSE- NO INTERRUPT
 *
 * Description        : get duty interrupt state.
 *
 * \endverbatim
 *******************************************************************************************************/
boolean Mcu_Ip_CkgenCqmGetDutyIntState(uint32 base, uint32 cqmIndex);

/** *****************************************************************************************************
 * \brief get jitter interrupt state.
 *
 * \verbatim
 * Syntax             : boolean Mcu_Ip_CkgenCqmGetJitterIntState(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : TRUE- INTERRUPT, FALSE- NO INTERRUPT
 *
 * Description        : get duty interrupt state.
 *
 * \endverbatim
 *******************************************************************************************************/
boolean Mcu_Ip_CkgenCqmGetJitterIntState(uint32 base, uint32 cqmIndex);

/** *****************************************************************************************************
 * \brief clear duty interrupt state.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenCqmClearDutyIntState(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : clear duty interrupt state.
 *
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenCqmClearDutyIntState(uint32 base, uint32 cqmIndex);

/** *****************************************************************************************************
 * \brief clear jitter interrupt state.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenCqmClearJitterIntState(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : clear jitter interrupt state.
 *
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenCqmClearJitterIntState(uint32 base, uint32 cqmIndex);

/** *****************************************************************************************************
 * \brief Setting the ip slice monitoring threshold
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenIpMonSetThrd(uint32 base, uint32 id,
                                      uint16 lowThrd, uint16 highThrd)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - slice id
 *                      lowThrd - lowThrd
 *                      highThrd - highThrd
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : Setting the yp slice monitoring threshold
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenIpMonSetThrd(uint32 base, uint32 id, uint16 lowThrd, uint16 highThrd);
/** *****************************************************************************************************
 * \brief Setting the bus slice monitoring threshold
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenBusMonSetThrd(uint32 base, uint32 type, uint32 id,
                               uint16 lowThrd, uint16 highThrd)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - slice id
 *                      lowThrd - lowThrd
 *                      highThrd - highThrd
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : Setting the bus slice monitoring threshold
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenBusMonSetThrd(uint32 base, uint32 type, uint32 id,
                               uint16 lowThrd, uint16 highThrd);

/** *****************************************************************************************************
 * \brief Setting the dbgMon monitoring threshold
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenDbgMonSetThrd(uint32 base, uint16 lowThrd, uint16 highThrd)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      lowThrd - lowThrd
 *                      highThrd - highThrd
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : Setting the dbgMon monitoring threshold
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenDbgMonSetThrd(uint32 base, uint16 lowThrd, uint16 highThrd);

/** *****************************************************************************************************
 * \brief Setting the 24M/32K monitoring threshold
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_Ckgen24MMonSetThrd(uint32 base,
                                      uint16 lowThrd, uint16 highThrd)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      lowThrd - lowThrd
 *                      highThrd - highThrd
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : Setting the 24M/32K monitoring threshold
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_Ckgen24MMonSetThrd(uint32 base, uint16 lowThrd, uint16 highThrd);

/** *****************************************************************************************************
 * \brief Get Monitor Moudel Freq interface
 *
 * \verbatim
 * Syntax             : uint32 Mcu_Ip_CkgenGetMonitorClock(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex,
                                                                    uint32 rate)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      sliceType - sliceType
 *                      typeIndex - slcie index
 *                      rate - Expected frequency
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : real rate
 *
 * Description        : get the monitoring rate
 *                      Using 24M/div/2 as the monitoring frequency,
 *                      the number of waveforms at the monitored frequency during this period is recorded in the registers
 *                      and used to calculate the monitored frequency.
 *                      if clock loss happened, the recorded value will be cleaned.
 *                      if expected frequency less than 1M, need switch divnum
 * \endverbatim
 *******************************************************************************************************/
uint32 Mcu_Ip_CkgenGetMonitorClock(uint32 base, Mcu_CkgenType sliceType, uint32 typeIndex,
                                   uint32 rate);

/** *****************************************************************************************************
 * \brief Get DbgMon Monitor Moudel Freq interface
 *
 * \verbatim
 * Syntax             : uint32 Mcu_Ip_CkgenGetDbgMonClock(uint32 base, uint32 rate)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      sliceType - sliceType
 *                      typeIndex - slcie index
 *                      rate - Expected frequency
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : real rate
 *
 * Description        : Get DbgMon Monitor Moudel Freq interface
 *                      Using 24M/div/2 as the monitoring frequency,
 *                      the number of waveforms at the monitored frequency during this period is recorded in the registers
 *                      and used to calculate the monitored frequency.
 *                      if clock loss happened, the recorded value will be cleaned.
 *                      if expected frequency less than 1M, need switch divnum
 * \endverbatim
 *******************************************************************************************************/
uint32 Mcu_Ip_CkgenGetDbgMonClock(uint32 base, uint32 rate);
/** *****************************************************************************************************
 * \brief get the ip slice monitoring rate
 *
 * \verbatim
 * Syntax             : Mcu_CkgenRateType Mcu_Ip_CkgenIpMonGetRate(uint32 base, uint32 id)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - slice id
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : ip slice monitoring rate
 *
 * Description        : get the ip slice monitoring rate
 *                      Using 24M/div/2 as the monitoring frequency, clk_24m_mona/clk_24m_monb are used for clock frequency monitor.
 *                      the number of waveforms at the monitored frequency during this period is recorded in the registers
 *                      and used to calculate the monitored frequency.
 *                      if clock loss happened, the recorded value will be cleaned.
 * \endverbatim
 *******************************************************************************************************/
Mcu_CkgenRateType Mcu_Ip_CkgenIpMonGetRate(uint32 base, uint32 id, Mcu_ClkRateType rate);

/** *****************************************************************************************************
 * \brief get the bus slice monitoring rate
 *
 * \verbatim
 * Syntax             : Mcu_CkgenRateType Mcu_Ip_CkgenBusMonGetRate(uint32 base, uint32 id, uint32 type)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      id - slice id
 *                      type - MNPQ type
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : bus slice monitoring rate
 *
 * Description        : get the bus slice monitoring rate
 *                      Using 24M/div/2 as the monitoring frequency, clk_24m_mona/clk_24m_monb are used for clock frequency monitor.
 *                      the number of waveforms at the monitored frequency during this period is recorded in the registers
 *                      and used to calculate the monitored frequency.
 *                      if clock loss happened, the recorded value will be cleaned.
 * \endverbatim
 *******************************************************************************************************/
Mcu_CkgenRateType Mcu_Ip_CkgenBusMonGetRate(uint32 base, uint32 id, uint32 type, uint32 rate);

/** *****************************************************************************************************
 * \brief get the 24M/32K monitoring rate
 *
 * \verbatim
 * Syntax             : uint32 Mcu_Ip_Ckgen24MMonGetRate(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : ip slice monitoring rate
 *
 * Description        : get the 24M/32K monitoring rate
 *                      Using 24M/32K as monitoring frequency for each other,
 *                      the number of waveforms at the monitored frequency during this period is recorded in the registers
 *                      and used to calculate the monitored frequency.
 *                      if clock loss happened, the recorded value will be cleaned.
 * \endverbatim
 *******************************************************************************************************/
uint32 Mcu_Ip_Ckgen24MMonGetRate(uint32 base);
/** *****************************************************************************************************
 * \brief get the dbgMon monitoring rate
 *
 * \verbatim
 * Syntax             : Mcu_CkgenRateType Mcu_Ip_CkgenDbgMonGetRate(uint32 base, uint32 type, uint32 id, Mcu_ClkRateType rate)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      type - slice type
 *                      id - slice index
 *                      rate - expect rate
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : ip slice monitoring rate
 *
 * Description        : get the dbgMon monitoring rate
 *                      Using 24M/div/2 as the monitoring frequency, clk_24m_mona/clk_24m_monb are used for clock frequency monitor.
 *                      the number of waveforms at the monitored frequency during this period is recorded in the registers
 *                      and used to calculate the monitored frequency.
 *                      if clock loss happened, the recorded value will be cleaned.
 * \endverbatim
 *******************************************************************************************************/
Mcu_CkgenRateType Mcu_Ip_CkgenDbgMonGetRate(uint32 base, uint32 type, uint32 id,
        Mcu_ClkRateType rate);
/** *****************************************************************************************************
 * \brief This function used for enable/disable slice frequency monitor.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_CkgenMonEnable(uint32 base, Mcu_CkgenType type, uint32 id, boolean enable)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - ckgen base
 *                      type - slice type
 *                      id - slice index
 *                      timeout - wdt timeout
 *                      enable - TRUE: enable, FALSE: disable
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This function used for enable/disable slice frequency monitor.
 * \endverbatim
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_CkgenMonEnable(uint32 base, Mcu_CkgenType type, uint32 id, uint32 timeout,
                                     boolean enable);

/** *****************************************************************************************************
 * \brief This function used for enable/disable dbgMon frequency monitor.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_CkgenDbgMonEnable(uint32 base, boolean enable)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - ckgen base
 *                      enable - TRUE: enable, FALSE: disable
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This function used for enable/disable dbgMon frequency monitor.
 * \endverbatim
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_CkgenDbgMonEnable(uint32 base, boolean enable);
/** *****************************************************************************************************
 * \brief config duty and jitter, enable/disable cqm monitor.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_CkgenCqmEnable(uint32 base, uint16 duty, uint16 jitter, boolean enable)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - CKGEN base address
 *                      duty - duty
 *                      jitter - jitter
 *                      enable - TRUE/FALSE
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : config duty and jitter, enable/disable cqm monitor.
 *
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_CkgenCqmEnable(uint32 base, uint32 cqmIndex, uint16 duty, uint16 jitter,
                           boolean enable);
#endif /* MCU_CKGEN_H */
/* End of file */
